ZHCSJH7 March 2019 DS90UB940N-Q1
PRODUCTION DATA.
Figure 1. Checkerboard Data Pattern
Figure 2. CML Output Driver
Figure 3. LVCMOS Transition Times
Figure 4. PLL Lock Time
Figure 5. FPD-Link III Receiver DC VTH/VTL Definition
Figure 6. Output Data Valid (Setup and Hold) Times
Figure 7. BIST PASS Waveform
Figure 8. Serial Control Bus Timing Diagram
Figure 9. I2S Timing
Figure 10. Clock and Data Timing in HS Transmission
Figure 11. High-Speed Data Transmission Burst
Figure 12. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
Figure 13. Long Line Packets and Short Frame Sync Packets
Figure 14. 4 MIPI® Data Lane Configuration
Figure 15. 2 MIPI® Data Lane Configuration