ZHCSJH7 March 2019 DS90UB940N-Q1
PRODUCTION DATA.
The BIST mode is enabled at the deserializer by the BISTEN pin or the BIST configuration register. The test may select either an external PCLK or the 33-MHz internal oscillator clock (OSC) frequency in the serializer. In the absence of PCLK, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors the pattern for errors. The deserializer PASS output pin toggles to flag each frame received that contains one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame.
The BIST status can be monitored in real time on the deserializer PASS pin, and each detected error results in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until a reset is triggered by a new BIST test or a power down. A high on PASS indicates that NO ERRORS were detected. A Low on PASS indicates that one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 26 for the BIST mode flow diagram.