ZHCSOU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
The power-up sequence for the DS90UB638-Q1 is as follows:
| PARAMETER | MIN | TYP | MAX | UNIT | NOTES | |
|---|---|---|---|---|---|---|
| T0 | VDD18 rise time | 0.05 | ms | at 10/90% | ||
| T1 | VDDIO rise time | 0.2 | 1 | ms | at 10/90% | |
| T2 | VDD18 High to VDD11 applied | 0 | ms | N/A when VDD_SEL = LOW | ||
| T3 | VDD11 rise time | 0.2 | 1 | ms | at 10/90% | |
| T4 | VDD to PDB | 0 | ms | After all VDD are stable | ||
| T5 | PDB high time before PDB hard reset | 1 | ms | |||
| T6 | PDB high to low pulse width | 2 | ms | Hard reset (optional) | ||
| T7 | PDB to I2C ready (IDX and MODE valid) delay | 2 | ms | |||