ZHCSOU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
The AEQ circuit can be restarted at any time by setting the AEQ_RESTART bit in the AEQ_CTL2 register 0xD2 (see Table 7-141). Once the deserializer is powered on, the AEQ is continually searching through EQ settings and could be at any setting when signal is supplied from the serializer. If the Rx Port CDR locks to the signal, it may be good enough for low bit errors, but could be not optimized or overequalized. The DS90UB638-Q1 when connected to an ADAS serializer (DS90UB63x-Q1) will by default restart the AEQ adaption upon achieving first positive lock indication in order to provide more consistent start-up from known conditions. With this feature disabled, the AEQ may lock at a relatively random EQ setting based on when the FPD-Link III input signal is initially present. Alternatively, AEQ_RESTART or DIGITAL_RESET0 could be applied once the ADAS serializer input signal frequency is stable to restart adaption from the minimum EQ gain value. These techniques allow for a more consistent initial EQ setting following adaption.