ZHCSOU1 February 2023 DS90UB638-Q1
PRODUCTION DATA
The DS90UB638-Q1 provides dedicated PASS and LOCK outputs for monitoring status as well as through the DEVICE_STS register (address 0x04).The source of the deserializer LOCK and PASS signals for pin monitoring and interrupt operation is also controlled by the LOCK_SEL and PASS_SEL fields in the RX_PORT_CTL register. The source of the LOCK and PASS can be allocated to Port 0 Receiver. At start-up, the deserializer will synchronize with the input signal provided by the serializer and assert the LOCK indication once stable. The lock detect circuit includes an option to check for link bit errors as part of the lock detection and determine if LOCK is lost. The Receive Port Lock status is available through the RX_PORT_STS1 register 0x4D. The LOCK status may also be used to enable video forwarding and other options. I2C communication across the FPD-Link should be attempted only during LOCK condition.
If the deserializer loses LOCK, the receiver will reset and perform the LOCK algorithm again to reacquire the serial data stream sent by the serializer. The receive port will truncate video frames containing errors and resume forwarding the video when LOCK is re-established.
The Receive port will indicate Pass status once specific conditions are met, including a number of valid frames received. Valid frames may include requiring no link bit errors and consistent frame size including video line length or number of video lines. The receive port may be programmed to truncate video frames containing errors and prevent the forwarding of video until the Pass conditions are met.