ZHCSKE9C December 2015 – October 2019 DS250DF810
PRODUCTION DATA.
The following example layout demonstrates how all signals can be escaped from the BGA array using stripline routing on a generic 28-layer stackup. This example layout assumes the following:
Note that many other escape routing options exist using different trace width and spacing combinations. The optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.
Figure 20. Top Layer
Figure 22. Internal Signal Layer 2
Figure 21. Internal Signal layer 1
Figure 23. Bottom Layer