ZHCSKE9C December 2015 – October 2019 DS250DF810
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CLKf | Calibration clock frequency | 25 | MHz | |||
| CLKPPM | Calibration clock PPM tolerance | -100 | 100 | PPM | ||
| CLKIDC | Recommended/tolerable input duty cycle | 40% | 50% | 60% | ||
| CLKODC | Intrinsic calibration clock duty cycle distortion | Intrinsic duty cycle distortion of chip calibration clock output at the CAL_CLK_OUT pin, assuming 50% duty cycle on CAL_CLK_IN pin. | 45% | 55% | ||
| CLKnum | Number of devices which can be cascaded from CAL_CLK_OUT to CAL_CLK_IN | Assumes worst-case 60%/40% input duty cycle on the first device. CAL_CLK_OUT from first devuce connects to CAL_CLK_IN of second device, and so on until the last device. | 20 | N/A | ||