ZHCSKE8D March 2016 – October 2019 DS250DF410
PRODUCTION DATA.
The following example layout demonstrates how all signals can be escaped from the BGA array using microstrip routing on a generic multi-layer stackup. This example layout assumes the following:
Note that many other escape routing options exist using different trace width and spacing combinations. The optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.
Figure 25. Top Layer
Figure 27. Internal Low-Speed Signal Layers
Figure 29. Bottom Layer
Figure 26. Layer 1 GND
Figure 28. VDD Layer