ZHCSKE8D March   2016  – October 2019 DS250DF410

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用
3. 3 說(shuō)明
   1.     Device Images
      1.      簡(jiǎn)化原理圖
4. 4 修訂歷史記錄
5. 5 說(shuō)明 （續(xù)）
6. 6 Pin Configuration and Functions
   1.     Pin Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  Electrical Characteristics
   6. 7.6  Timing Requirements, Retimer Jitter Specifications
   7. 7.7  Timing Requirements, Retimer Specifications
   8. 7.8  Timing Requirements, Recommended Calibration Clock Specifications
   9. 7.9  Recommended SMBus Switching Characteristics (Slave Mode)
   10. 7.10 Recommended SMBus Switching Characteristics (Master Mode)
   11. 7.11 Recommended JTAG Switching Characteristics
   12. 7.12 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver with FIR Filter
         1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
         2. 8.3.9.2 Output Driver Polarity Inversion
      10. 8.3.10 Debug Features
          1. 8.3.10.1 Pattern Generator
          2. 8.3.10.2 Pattern Checker
          3. 8.3.10.3 Eye Opening Monitor
      11. 8.3.11 Interrupt Signals
      12. 8.3.12 JTAG Boundary Scan
   4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
   5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
   6. 8.6 Register Maps
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Detailed Design Procedure
         3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
         1. 9.2.2.1 Design Requirements
         2. 9.2.2.2 Detailed Design Procedure
         3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-plane Applications
         1. 9.2.3.1 Design Requirements
         2. 9.2.3.2 Detailed Design Procedure
         3. 9.2.3.3 Application Curves
10. 10Power Supply Recommendations
11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
12. 12器件和文檔支持
    1. 12.1 文檔支持
       1. 12.1.1 開(kāi)發(fā)支持
    2. 12.2 文檔支持
       1. 12.2.1 相關(guān)文檔
    3. 12.3 接收文檔更新通知
    4. 12.4 支持資源
    5. 12.5 商標(biāo)
    6. 12.6 靜電放電警告
    7. 12.7 Glossary
13. 13機(jī)械、封裝和可訂購(gòu)信息