ZHCSKE8D March 2016 – October 2019 DS250DF410
PRODUCTION DATA.
The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates. The host should provide an input calibration clock signal of 25 MHz frequency. Because this clock is not used for clock and data recovery, there are no stringent jitter requirements placed on this 25 MHz calibration clock.