ZHCSKE8D March 2016 – October 2019 DS250DF410
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| JTJ | Output total jitter (TJ) | Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded. | 0.17 | UIpp @ 1E-12 | ||
| JRJ | Output random Jitter (RJ) | Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded | 6 | mUI RMS | ||
| JDCD | Output duty cycle distortion (DCD) | Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded | 4 | mUIpp | ||
| JPEAK | Jitter peaking | Measured at 10.3125 Gbps with PRBS7 data pattern. Peaking frequency in the range of 1 to 6 MHz. | 0.8 | dB | ||
| JPEAK | Jitter peaking | Measured at 25.78125 Gbps with PRBS7 data pattern. Peaking frequency in the range of 1 to 17 MHz. | 0.4 | dB | ||
| BWPLL | PLL bandwidth | Data rate of 10.3125Gbps with PRBS7 pattern | 5.3 | MHz | ||
| BWPLL | PLL bandwidth | Data rate of 25.78125Gbps with PRBS7 pattern | 5.5 | MHz | ||
| JTOL | Input jitter tolerance | Measured at 25.78125 Gbps with SJ frequency = 190 KHz, 30dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. | 9 | UIpp | ||
| JTOL | Input jitter tolerance | Measured at 25.78125 Gbps with SJ frequency = 940 KHz, 30dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. | 1 | UIpp | ||
| JTOL | Input jitter tolerance | Measured at 25.78125 Gbps with SJ frequency > 15MHz, 30dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. | 0.3 | UIpp | ||
| TEMPLOCK- | CDR stay-in-lock ambient temperature range, negative ramp. Maximum temperature change below initial CDR lock acquisition temperature. | 85 °C starting ambient temperature, ramp rate -3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB. | 115 | °C | ||
| TEMPLOCK+ | CDR stay-in-lock ambient temperature range, positive ramp. Maximum temperature change above initial CDR lock acquisition temperature. | -40 °C starting ambient temperature, ramp rate +3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB. | 125 | °C | ||