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ZHCSKE8D March 2016 – October 2019 DS250DF410

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

ABM|101
- MPBGAL0B

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Rbaud	Input data rate	Full-rate	20.2752		25.8	Gbps
		Half-rate	10.1376		12.9	Gbps
		Quarter-rate	5.0688		6.45	Gbps
t_EEPROM	EEPROM configuration load time	Single device reading its configuration from an EEPROM. Common channel configuration. This time scales with the number of devices reading from the same EEPROM.			15⁽²⁾	ms
t_EEPROM	EEPROM configuration load time	Single device reading its configuration from an EEPROM. Unique channel configuration. This time scales with the number of devices reading from the same EEPROM.			40⁽²⁾	ms
t_POR	Power-on reset assertion time	Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted.			50	ms
POWER SUPPLY
W_channel	Power consumption per active channel	With CTLE, full DFE, Tx FIR, Driver, and Crosspoint enabled. Idle power consumption not included.		241	305	mW
		With CTLE, full DFE, Tx FIR, and Driver enabled; Crosspoint disabled. Idle power consumption not included.		233		mW
		With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; Crosspoint and DFE taps 3-5 disabled. Idle power consumption not included.		220		mW
		With CTLE, Tx FIR, Driver, and Crosspoint enabled; DFE disabled. Idle power consumption not included.		211	290	mW
		Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Crosspoint enabled. Idle power consumption not included.		365	430	mW
		Assuming CDR acquiring lock with CTLE, Tx FIR, Driver, and Crosspoint enabled; DFE disabled. Idle power consumption not included.		318	393	mW
		PRBS checker power consumption only⁽¹⁾		220	302	mW
		PRBS generator power power consumption only⁽¹⁾		230	315	mW
W_{static_total}	Total idle power consumption	Idle/static mode, power supplied, no high-speed data present at inputs, all channels automatically powered down.		329	525	mW
I_total	Active mode total device supply current consumption	With CTLE, full DFE, Tx FIR, Driver, and Crosspoint enabled.		518	665	mA
		With CTLE, full DFE, Tx FIR, and Driver enabled; Crosspoint disabled.		505		mA
		With CTLE, partial DFE (taps 1-2 only), Tx FIR, and Driver enabled; Crosspoint and DFE taps 3-5 disabled.		485		mA
		With CTLE, Tx FIR, Driver, and Crosspoint enabled. DFE disabled.		470	639	mA
I_{static_total}	Idle mode total device supply current consumption	Idle/static mode. Power supplied, no high-speed data present at inputs, all channels automatically powered down.		132	200	mA
LVCMOS DC SPECIFICATIONS
V_IH	Input high-level voltage	2.5-V LVCMOS pins	1.75		VDD	V
V_IH	Input high-level voltage	3.3-V LVCMOS pin (READ_EN_N)	1.75		3.6	V
V_IL	Input low-level voltage	2.5-V LVCMOS pins	GND		0.7	V
V_IL	Input low-level voltage	3.3-V LVCMOS pin (READ_EN_N)	GND		0.8	V
V_TH	High level (1) input voltage	4-level pins ADDR0, ADDR1, and EN_SMB		0.95 × VDD		V
	Float level input voltage	4-level pins ADDR0, ADDR1, and EN_SMB		0.67 × VDD		V
	10K to GND input voltage	4-level pins ADDR0, ADDR1, and EN_SMB		0.33 × VDD		V
	Low -evel (0) input voltage	4-level pins ADDR0, ADDR1, and EN_SMB		0.1		V
V_OH	High-level output voltage	IOH = 4 mA	2			V
V_OL	Low-level output voltage	IOL = –4 mA			0.4	V
I_IH	Input high leakage current	Vinput = VDD, Open drain pins			70	μA
I_IH	Input high leakage current	Vinput = VDD and CAL_CLK_IN pin			65	μA
I_IH	Input high leakage current	Vinput = VDD, ADDR[1:0] and EN_SMB pins			65	μA
I_IH	Input high leakage current	Vinput = VDD, READ_EN_N			15	μA
I_IL	Input low leakage current	Vinput = 0 V, Open drain pins	-15			μA
I_IL	Input low leakage current	Vinput = 0 V, CAL_CLK_IN pins	-15			μA
I_IL	Input low leakage current	Vinput = 0 V, ADDR[1:0], READ_EN_N, and EN_SMB pins	-115			μA
RECEIVER INPUTS (RXnP, RXnN)
V_IDMax	Maximum input differential voltage	For normal operation		1225		mVppd
RL_SDD11	Differential input return loss, SDD11⁽³⁾	Between 50 MHz and 3.69 GHz		<-18		dB
RL_SDD11	Differential input return loss, SDD11⁽³⁾	Between 3.69 GHz and 12.9 GHz		<-14		dB
RL_SDC11	Differential to common-mode input return loss, SDC11⁽³⁾	Between 50 MHz and 12.9 GHz		<-23		dB
RL_SCD11	Differential to common-mode input return loss, SCD11⁽³⁾	Between 50 MHz and 12.9 GHz		<-22		dB
RL_SCC11	Common-mode input return loss, SCC11⁽³⁾	Between 150 MHz and 10 GHz		<-11		dB
RL_SCC11	Common-mode input return loss, SCC11⁽³⁾	Between 10 GHz and 12.9 GHz		<-10		dB
V_SDAT	AC signal detect assert (ON) threshold level	Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. 25.78125Gbps with PRBS7 pattern and 20dB loss channel		196		mVppd
V_SDDT	AC signal detect de-assert (OFF) threshold level	Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. 25.78125Gbps with PRBS7 pattern and 20dB loss channel		147		mVppd
TRANSMITTER OUTPUTS (TXnP, TXnN)
VOD	Output differential voltage amplitude	Measured with c(0)=7 setting (Reg_0x3D[6:0]=0x07, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND.		525		mVppd
VOD	Output differential voltage amplitude	Measured with c(0)=31 setting (Reg_0x3D[6:0]=0x1F, Reg_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND.		1225		mVppd
VOD_idle	Differential output amplitude with TX disabled			< 11		mVppd
VOD_res	Output VOD resolution	Difference in VOD between two adjacent c(0) settings. Applies to VOD in the 525mVppd to 1225mVppd range [c(0)>4].		< 50		mVppd
V_cm-TX-AC	Common-mode AC output noise	With respect to signal ground. Measured with PRBS9 data pattern. Measured with a 33GHz (-3dB) low-pass filter.		6.5		mV, RMS
t_r, t_f	Output transition time	20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 25.78125 Gbps. Measured for ~800 mVppd output amplitude and no equalization: Reg_0x3D=+13, Reg_0x3E=0, REG_0x3F=0		17		ps
RL_SDD22	Differential output return loss, SDD22⁽⁴⁾	Between 50 MHz and 5 GHz		<-14		dB
RL_SDD22	Differential output return loss, SDD22⁽⁴⁾	Between 5 GHz and 12.9 GHz		<-13		dB
RL_SCD22	Common-mode to differential output return loss, SCD22⁽⁴⁾	Between 50 MHz and 12.9 GHz		<-22		dB
RL_SDC22	Differential-to-common-mode output return loss, SDC22⁽⁴⁾	Between 50 MHz and 12.9 GHz		<-22		dB
RL_SCC22	Common-mode output return loss, SCC22⁽⁴⁾	Between 50 MHz and 10 GHz		<-9		dB
RL_SCC22	Common-mode output return loss, SCC22⁽⁴⁾	Between 10 GHz and 12.9 GHz		<-12		dB
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
V_IH	Input high-level voltage	SDA and SDC	1.75		3.6	V
V_IL	Input low-level voltage	SDA and SDC	GND		0.8	V
C_IN	Input pin capacitance			15		pF
V_OL	Low-level output voltage	SDA or SDC, IOL = 1.25 mA			0.4	V
I_IN	Input current	SDA or SDC, VINPUT = VIN, VDD, GND	-15		15	μA
T_R	SDA rise time, read operation	Pull-up resistor = 1 kΩ, Cb = 50pF		150		ns
T_F	SDA fall time, read operation	Pull-up resistor = 1 kΩ, Cb = 50pF		4.5		ns

(1) To ensure optimal performance, it is recommended to not enable more than two PRBS blocks (checker and/or generator) per device.

(2) From low assertion of READ_EN_N to low assertion of ALL_DONE_N. Does not include Power-On Reset time.

(3) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 3 dB insertion loss at 12.9 GHz between the DS250DF410 and the measurement instrument.

(4) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 3 dB insertion loss at 12.9 GHz between the DS250DF410 and the measurement instrument.