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ZHCSCD5B April 2014 – January 2017 DS125DF1610

PRODUCTION DATA.

封裝選項

機械數(shù)據 (封裝 | 引腳)

ABB|196
- MPBGAF3B

散熱焊盤機械數(shù)據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Supply Voltage (VDD)	–0.5	2.75	V
LVCMOS Input/Output Voltage	–0.5	2.75	V
Open Drain I/O Supply Voltage	–0.5	4.0	V
CML Input Voltage	–0.5	(VDD + 0.5)	V
CML Input Current	–30	30	mA
Storage temperature range, T_stg	-40	150	°C

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications

6.2 Handling Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±4,000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1,000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

	MIN	TYP	MAX	UNIT
Supply Voltage	2.375	2.5	2.625	V
Ambient Temperature	–40	25	85	°C
SMBus (SDA, SCL), INTERR_IO		2.5	3.6	V
Maximum Continuous Junction Temperature while Device is Operational			115	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾ ⁽²⁾		DS125DF1610 FCBGA ABB (196) PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	18.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.7
R_θJB	Junction-to-board thermal resistance	5.3
ψ_JT	Junction-to-top characterization parameter	0.8
ψ_JB	Junction-to-board characterization parameter	5.3
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Thermal model available upon request

6.5 Additional Thermal Information

BOARD	θ_JC (°C / W)	θ_JA (°C / W)	ψ_JT(°C / W)	ψ_JB(°C / W)
JEDEC 4 layer board, no airflow	0.7	18.2	0.8	5.3
8x6 inches 10 layer, no airflow	0.7	7.2	0.3	3.2
8x6 inches 20 layer, no airflow	0.7	6.4	0.3	3.2
8x6 inches 30 layer, no airflow	0.7	6.3	0.3	3.2

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
R_baud	Input Data Rate	Full Rate	9.8		12.5	Gbps
		Half Rate	4.9		6.25	Gbps
		Quarter Rate	2.45		3.125	Gbps
		Eighth Rate	1.225		1.5625	Gbps
POWER SUPPLY
W	Power Consumption per Active Channel	CTLE only, 800mVp-p VOD, per channel, CDR locked		175		mW
		CDR Locking with CTLE only, 800mVp-p VOD, per channel		325		mW
		CTLE and DFE, 800mVp-p VOD, per channel, CDR locked		200	323	mW
		CDR Locking with CTLE and DFE, 800mVp-p VOD		350	535.5	mW
		PRBS Checker		100		mW
		PRBS Generator		105		mW
W_STATIC	Device Static Power Consumption	Power Applied to Device, No Signals Present		325	1325	mW
NT_PS	Power Supply Noise Tolerance	50 Hz to 100 Hz		100		mV_PP
		100 Hz to 10 MHz		40
		10 MHz to 5.0 GHz		10
LVCMOS
V _IH	High level input voltage		1.75		VDD	V
V_IL	Low level input voltage		GND		0.7	V
V_OH	High level output voltage	IOH = 4mA	2			V
V_OL	Low level output voltage	IOL = -4mA			0.4	V
I_IH	Input High Leakage current	Vinput = VDD, Open Drain terminals			30	µA
		Vinput = VDD, JTAG terminals, Ref_CLK terminals			25	µA
		Vinput = VDD, ADDR, READ_EN, ALL_DONE terminals, EN_SMB terminal			75	µA
I_IL	Input Low Leakage current	Vinput = 0V, Open drain terminals	-15			µA
		Vinput = 0V, JTAG terminals, Ref_CLK terminals	-45			µA
		Vinput = 0V, ADDR, READ_EN, ALL_DONE terminals, EN_SMB terminal	-120			µA
RX INPUTS
R_RD	DC Input Resistance		80	100	120	Ω
V_RX-IN	Input Differential Voltage	Differential voltage seen at the high speed input terminals ⁽²⁾			1600	mV_PP
V_SDAT	Signal Detect Assert Threshold	Default setting 1T pattern, 12.5 Gbps		110		mV_PP
V_SDAT	Signal Detect Assert Threshold	Default setting PRBS-31, 12.5 Gbps		24		mV_PP
V_SDDT	Signal Detect De-Assert Threshold	Default setting 1T pattern, 12.5 Gbps		70		mV_PP
V_SDDT	Signal Detect De-Assert Threshold	Default setting PRBS-31, 12.5 Gbps		21		mV_PP
V_cm-RX	Input common mode	Internal coupling cap	V_RX-IN / 4		VDD - (V_RX-IN/ 4)	V
TX OUTPUTS
V_OD	Output Differential Voltage	drv_sel_vod[5:0] = 31, DEM, FIR = default	725	935	1135	mV_PP
V_OD	Output Differential Voltage	drv_sel_vod[5:0] = 15, DEM, FIR = default	350	470	595	mV_PP
ΔV_OD	Step Size for drv_sel_vod Control	Default DEM, and FIR settings		50		mV_PP
ΔV_ODVT	Change in Output Differential Voltage due to Change in Temperature and Voltage			<15		mV_PP
T_Rd	Output Differential Resistance			100		Ω
t_r, t_f	Output Rise/Fall Time	20% - 80% using 8T Pattern, fir_sel_edge = default		35		ps
I_OS	Output Short Circuit Current	Differential Driver Output Pin Short to GND		-16		mA
RETIMER JITTER SPECS
J_TJ	Total Output Jitter	PRBS-15 pattern, measured to 1e-12 10.3125 Gbps		0.08		UI
J_RJ	Output Random Jitter	PRBS-15 pattern, measured to 1e-12 10.3125 Gbps		3.6		mUI_RMS
J_DJ	Output Deterministic Jitter	PRBS-15 10.3125 Gbps		0.03		UI
J_PEAK	Jitter Peaking	Data Rate = 9.8 Gbps, Peaking Frequency = 1 - 3 MHz		<1		dB
J_PEAK	Jitter Peaking	Data Rate = 12.5 Gbps Peaking Frequency = 3 - 8 MHz		<1		dB
BW_PLL	PLL Bandwidth at -3 dB	Data Rate = 9.8 Gbps		5		MHz
BW_PLL	PLL Bandwidth at -3 dB	Data Rate = 12.5 Gbps		10		MHz
J_TOL	Input Jitter Tolerance	Jitter per SFF-8431 Appendix D.11 Combination of D_J P_J and R_J		>0.7		UI
RETIMER TIMING SPECS
t_D	Propagation Delay from Rx inputs to Tx outputs	No Cross Point		3UI + 220ps		ps
t_D	Propagation Delay from Rx inputs to Tx outputs	Cross Point enabled		3UI + 230ps		ps
t_SK	Channel To Channel Skew			<80		ps
RECOMMENDED REFERENCE CLOCK SPECS
REF_f	Input Reference Clock Frequency			25		MHz
				125
				312.5
REF_PPM	Reference Clock PPM Tolerance	REF_f = 25 MHz⁽¹⁾	-100		100	PPM
REF_IDC	Input Reference Clock Duty Cycle	REF_f = 25 MHz⁽¹⁾	40%	50%	60%
REF_ODC	Intrinsic Reference Clock Duty Cycle Distortion	Intrinsic Duty Cycle Distortion of the reference clock output from the CLK_MON pins		±1%
REF_VID	Reference Clock Input Differential Voltage	Differential mode⁽¹⁾	200		1200	mV_PP
REF_VIH	Reference Clock Signle-Ended Input High Threshold	Single-ended mode. Signal DC coupled to REF_CLK_P, REF_CLK_N is float		1.75		V
REF_VIL	Reference Clock Single-Ended Input Low Threshold	Single-ended mode. Signal DC coupled to REF_CLK_P, REF_CLK_N is float		0.7		V
SMBus ELECTRICAL CHARACTERISTICS (SLAVE MODE)
V_IH	Input High Level Voltage	SDA and SCL	1.75		3.6	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.8	V
C_IN	Input Pin Capacitance			<5		pF
V_OL	Low Level Output Voltage	SDA or SCL IOL = 1.25 mA			0.4	V
I_IN	Input Current	SDA or SCL, V_INPUT = V_IN, V_DD, GND	-15		15	µA
T_R	SDA Rise Time Read Operation	SDA, pullup resistor = 1 kΩ, Cb = 50pF		150		ns
T_F	SDA Fall Time Read Operation	SDA, pullup resistor = 1 kΩ, Cb = 50pF		4.5		ns
RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SLAVE MODE)
f_SCL	SCL Clock Frequency		10	100	400	kHz
t_HD:DAT	Data Hold Time			0.75		ns
t_SU:DAT	Data Setup Time			100		ns
RECOMMENDED SMBus SWITCHING CHARACTERISTICS (MASTER MODE)
F_SCL	SCL Clock Frequency			400		kHz
T_LOW	SCL Low Period			1.25		µs
T_HIGH	SCL High Period			1.25		µs
T_HD:STA	Hold Time Start Operation			0.6		µs
T_SU:STA	Setup Time Start Operation			0.6		µs
T_HD:DAT	Data Hold Time			0.9		µs
T_SD:DAT	Data Setup Time			0.1		µs
T_SU:STO	Stop Condition Setup Time			0.6		µs
T_BUF	Bus Free Time between Stop-Start			1.3		µs
T_R	SCL and SDA Rise Time			300		ns
T_F	SCL and SDA Fall Time			300		ns
RECOMMENDED JTAG SWITCHING CHARACTERISTICS
t_TCK	TCK Clock Period			100		ns
t_SU	TDI, TMI Setup Time to TCK			50		ns
t_HD	TDI, TMS Hold Time to TCK			50		ns
t_DLY	TCK Falling Edge to TDO			50		ns

(1) Parameter is specified by design and not tested at final production

(2) Parameter is not tested at final production

封裝選項

機械數(shù)據 (封裝 | 引腳)

散熱焊盤機械數(shù)據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

6.2 Handling Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Additional Thermal Information

6.6 Electrical Characteristics

6.1 Absolute Maximum Ratings⁽¹⁾