ZHCSJB5B September 2019 – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
| nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
| nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
| nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
| OUT1 | 2 | O | Half-bridge 1 output |
| OUT2 | 23 | O | Half-bridge 2 output |
| OUT3 | 14 | O | Half-bridge 3 output |
| OUT4 | 11 | O | Half-bridge 4 output |
| OUT5 | 3 | O | Half-bridge 5 output |
| OUT6 | 10 | O | Half-bridge 6 output |
| OUT7 | 4 | O | Half-bridge 7 output |
| OUT8 | 22 | O | Half-bridge 8 output |
| OUT9 | 9 | O | Half-bridge 9 output |
| OUT10 | 15 | O | Half-bridge 10 output |
| OUT11 | 17 | O | Half-bridge 11 output |
| OUT12 | 18 | O | Half-bridge 12 output |
| SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
| SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
| SDO | 7 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
| VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
| VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
| NC | 17 | — | Not connected |
| NC | 18 | — | Not connected |
| nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
| nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
| nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
| OUT1 | 2 | O | Half-bridge 1 output |
| OUT2 | 23 | O | Half-bridge 2 output |
| OUT3 | 14 | O | Half-bridge 3 output |
| OUT4 | 11 | O | Half-bridge 4 output |
| OUT5 | 3 | O | Half-bridge 5 output |
| OUT6 | 10 | O | Half-bridge 6 output |
| OUT7 | 4 | O | Half-bridge 7 output |
| OUT8 | 22 | O | Half-bridge 8 output |
| OUT9 | 9 | O | Half-bridge 9 output |
| OUT10 | 15 | O | Half-bridge 10 output |
| SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
| SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
| SDO | 7 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
| VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
| VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
| NC | 9 | — | Not connected |
| NC | 15 | — | Not connected |
| NC | 17 | — | Not connected |
| NC | 18 | — | Not connected |
| nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
| nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
| nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
| OUT1 | 2 | O | Half-bridge 1 output |
| OUT2 | 23 | O | Half-bridge 2 output |
| OUT3 | 14 | O | Half-bridge 3 output |
| OUT4 | 11 | O | Half-bridge 4 output |
| OUT5 | 3 | O | Half-bridge 5 output |
| OUT6 | 10 | O | Half-bridge 6 output |
| OUT7 | 4 | O | Half-bridge 7 output |
| OUT8 | 22 | O | Half-bridge 8 output |
| SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
| SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
| SDO | 7 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
| VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
| VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
| NC | 4 | — | Not connected |
| NC | 9 | — | Not connected |
| NC | 15 | — | Not connected |
| NC | 17 | — | Not connected |
| NC | 18 | — | Not connected |
| NC | 22 | — | Not connected |
| nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
| nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
| nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
| OUT1 | 2 | O | Half-bridge 1 output |
| OUT2 | 23 | O | Half-bridge 2 output |
| OUT3 | 14 | O | Half-bridge 3 output |
| OUT4 | 11 | O | Half-bridge 4 output |
| OUT5 | 3 | O | Half-bridge 5 output |
| OUT6 | 10 | O | Half-bridge 6 output |
| SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
| SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
| SDO | 7 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
| VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
| VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| GND | 13 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 24 | PWR | Device power ground. Connect the GND pin to the system ground. |
| GND | 1 | PWR | Device power ground. Connect the GND pin to the system ground. |
| NC | 3 | — | Not connected |
| NC | 4 | — | Not connected |
| NC | 9 | — | Not connected |
| NC | 10 | — | Not connected |
| NC | 15 | — | Not connected |
| NC | 17 | — | Not connected |
| NC | 18 | — | Not connected |
| NC | 22 | — | Not connected |
| nFAULT | 12 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor. |
| nSCS | 19 | I | Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up. |
| nSLEEP | 8 | I | Driver enable pin. When this pin is logic low the device goes to a low-power sleep mode. Internal pull-down. |
| OUT1 | 2 | O | Half-bridge 1 output |
| OUT2 | 23 | O | Half-bridge 2 output |
| OUT3 | 14 | O | Half-bridge 3 output |
| OUT4 | 11 | O | Half-bridge 4 output |
| SCLK | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down. |
| SDI | 5 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down. |
| SDO | 7 | PP | Serial data output. Data is shifted out on the rising edge of the SCLK pin. |
| VDD | 6 | PWR | Logic power supply input. Connect a X5R or X7R, 0.1-μF, VDD-rated ceramic capacitor and greater than or equal to 1-μF bulk capacitance between the VDD and GND pins. |
| VM | 16 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |
| VM | 21 | PWR | Main power supply input. Connect all VM pins together to the motor supply voltage. Connect a X5R or X7R, 0.1-μF, VM-rated ceramic capacitor and greater than or equal to 10-μF bulk capacitance between the VM and GND pins. |