SLVSBW9C April 2013 – December 2015 DRV8832-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The DRV8832-Q1 is active when either IN1 or IN2 are set to a logic high. Sleep mode is entered when both IN1 and IN2 are set to a logic low. When in sleep mode, the H-bridge FETs are disabled (Hi-Z).
| FAULT | CONDITION | H-BRIDGE | INTERNAL CIRCUITS | |
|---|---|---|---|---|
| Operating | IN1 or IN2 high | Operating | Operating | |
| Sleep mode | IN1 or IN2 low | Disabled | Diabled | |
| Fault encountered | Any fault condition met | Disabled | See Table 2 | |