7.5.1.1 Serial Peripheral Interface (SPI)
The SPI (DRV8703D-Q1 only) is used to set device configurations, operating parameters, and read out diagnostic information. The DRV8703D-Q1 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16-bit word, with a 5-bit command, 3 don't care bits, and 8 bits of data. The SPI output data (SDO) word consists of 8-bit register data and the first 8 bits are don’t cares.
A valid frame has to meet following conditions:
- The clock polarity (CPOL) must be set to 0.
- The clock phase (CPHA) must be set to 0.
- The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
- No SCLK signal can occur when the nSCS signal is in transition.
- The SCLK pin must be low when the nSCS pin goes high.
- The nSCS pin should be taken high for at least 500 ns between frames.
- When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is in the high impedance state.
- Full 16 SCLK cycles must occur.
- Data is captured on the falling edge of the clock and data is driven on the rising edge of the clock.
- The most-significant bit (MSB) is shifted in and out first
- For a write command, if the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word is ignored.
- For a write command, the existing data in the register being written to is shifted out on the SDO pin following the 5-bit command data