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ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTA|40
- MPQF134A

散熱焊盤機械數據 (封裝 | 引腳)

RTA|40
- QFND055H

訂購信息

7.5 Electrical Characteristics

at T_A = –40°C to +125°C, V_VM = 9 to 75 V, V_VDRAIN = 9 to 100 V, V_VIN = 48 V (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
I_VM	VM operating supply current		V_VM = V_VDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V		8.5	13	mA
I_VDRAIN	VDRAIN operating supply current		V_VM = V_VDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V		1.9	4	mA
I_SLEEP	Sleep mode supply current		ENABLE = 0 V, V_VM = V_VDRAIN = 48 V, T_A = 25°C		20	40	µA
I_SLEEP	Sleep mode supply current		ENABLE = 0 V, V_VM = V_VDRAIN = 48 V, T_A = 125°C			100	µA
t_RST	Reset pulse time		ENABLE = 0 V period to reset faults	5		40	µs
t_WAKE	Turnon time		V_VM > V_UVLO, ENABLE = 3.3 V to outputs ready			1	ms
t_SLEEP	Turnoff time		ENABLE = 0 V to device sleep mode			1	ms
V_DVDD	DVDD regulator voltage		I_DVDD = 0 to 10 mA	4.75	5	5.25	V
V_VCP	VCP operating voltage with respect to VDRAIN		V_VM = 15 V, I_VCP = 0 to 25 mA	9	10.5	12	V
			V_VM = 12 V, I_VCP = 0 to 20 mA	7.5	10	11.5
			V_VM = 10 V, I_VCP = 0 to 15 mA	6	8	9.5
			V_VM = 9 V, I_VCP = 0 to 10 mA	5.5	7.5	8.5
V_VGLS	VGLS operating voltage with respect to GND		V_VM = 15 V, I_VGLS = 0 to 25 mA	13	14.5	16	V
			V_VM = 12 V, I_VGLS = 0 to 20 mA	10	11.5	12.5
			V_VM = 10 V, I_VGLS = 0 to 15 mA	8	9.5	10.5
			V_VM = 9 V, I_VGLS = 0 to 10 mA	7	8.5	9.5
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
V_IL	Input logic low voltage			0		0.8	V
V_IH	Input logic high voltage			1.5		5.5	V
V_HYS	Input logic hysteresis				100		mV
I_IL	Input logic low current		V_VIN = 0 V	–5		5	µA
I_IH	Input logic high current		V_VIN = 5 V		50	70	µA
R_PD	Pulldown resistance		To GND		100		kΩ
t_PD	Propagation delay		INHx/INLx transition to GHx/GLx transition		200		ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
V_I1	Input mode 1 voltage		Tied to GND		0		V
V_I2	Input mode 2 voltage		47 kΩ ± 5% to tied GND		1.9		V
V_I3	Input mode 3 voltage		Hi-Z		3.1		V
V_I4	Input mode 4 voltage		Tied to DVDD		5		V
R_PU	Pullup resistance		Internal pullup to DVDD		50		kΩ
R_PD	Pulldown resistance		Internal pulldown to GND		84		kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
V_I1	Input mode 1 voltage		Tied to GND		0		V
V_I2	Input mode 2 voltage		18 kΩ ± 5% tied to GND		0.8		V
V_I3	Input mode 3 voltage		75 kΩ ± 5% tied to GND		1.7		V
V_I4	Input mode 4 voltage		Hi-Z		2.5		V
V_I5	Input mode 5 voltage		75 kΩ ± 5% tied to DVDD		3.3		V
V_I6	Input mode 6 voltage		18 kΩ ± 5% tied to DVDD		4.2		V
V_I7	Input mode 7 voltage		Tied to DVDD		5		V
R_PU	Pullup resistance		Internal pullup to DVDD		73		kΩ
R_PD	Pulldown resistance		Internal pulldown to GND		73		kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
V_OL	Output logic low voltage		I_O = 5 mA			0.125	V
I_OZ	Output high impedance leakage		V_O = 5 V	–2		2	µA
GATE DRIVERS (GHx, GLx)
V_GSH	High-side gate drive voltage with respect to SHx		V_VM = 15 V, I_VCP = 0 to 25 mA	9	10.5	12	V
			V_VM = 12 , I_VCP = 0 to 20 mA	7.5	10	11.5
			V_VM = 10 V, I_VCP = 0 to 15 mA	6	8	9.5
			V_VM = 9 V, I_VCP = 0 to 10 mA	5.5	7.5	8.5
V_GSL	Low-side gate drive voltage with respect to PGND		V_VM = 15 V, I_VGLS = 0 to 25 mA	9.5	11	12.5	V
			V_VM = 12 V, I_VGLS = 0 to 20 mA	9	10.5	12
			V_VM = 10 V, I_VGLS = 0 to 15 mA	7.5	9	10.5
			V_VM = 9 V, I_VGLS = 0 to 10 mA	6.5	8	9.5
t_DEAD	Gate drive dead time	SPI Device	DEAD_TIME = 00b		50		ns
			DEAD_TIME = 01b		100
			DEAD_TIME = 10b		200
			DEAD_TIME = 11b		400
		H/W Device			100
t_DRIVE	Peak current gate drive time	SPI Device	TDRIVE = 00b		500		ns
			TDRIVE = 01b		1000
			TDRIVE = 10b		2000
			TDRIVE = 11b		4000
		H/W Device			4000
I_DRIVEP	Peak source gate current	SPI Device	IDRIVEP_HS or IDRIVEP_LS = 0000b		50		mA
			IDRIVEP_HS or IDRIVEP_LS = 0001b		50
			IDRIVEP_HS or IDRIVEP_LS = 0010b		100
			IDRIVEP_HS or IDRIVEP_LS = 0011b		150
			IDRIVEP_HS or IDRIVEP_LS = 0100b		300
			IDRIVEP_HS or IDRIVEP_LS = 0101b		350
			IDRIVEP_HS or IDRIVEP_LS = 0110b		400
			IDRIVEP_HS or IDRIVEP_LS = 0111b		450
			IDRIVEP_HS or IDRIVEP_LS = 1000b		550
			IDRIVEP_HS or IDRIVEP_LS = 1001b		600
			IDRIVEP_HS or IDRIVEP_LS = 1010b		650
			IDRIVEP_HS or IDRIVEP_LS = 1011b		700
			IDRIVEP_HS or IDRIVEP_LS = 1100b		850
			IDRIVEP_HS or IDRIVEP_LS = 1101b		900
			IDRIVEP_HS or IDRIVEP_LS = 1110b		950
			IDRIVEP_HS or IDRIVEP_LS = 1111b		1000
		H/W Device	IDRIVE = Tied to GND		50
			IDRIVE = 18 kΩ ± 5% tied to GND		100
			IDRIVE = 75 kΩ ± 5% tied to GND		150
			IDRIVE = Hi-Z		300
			IDRIVE = 75 kΩ ± 5% tied to DVDD		450
			IDRIVE = 18 kΩ ± 5% tied to DVDD		700
			IDRIVE = Tied to DVDD		1000
I_DRIVEN	Peak sink gate current	SPI Device	IDRIVEN_HS or IDRIVEN_LS = 0000b		100		mA
			IDRIVEN_HS or IDRIVEN_LS = 0001b		100
			IDRIVEN_HS or IDRIVEN_LS = 0010b		200
			IDRIVEN_HS or IDRIVEN_LS = 0011b		300
			IDRIVEN_HS or IDRIVEN_LS = 0100b		600
			IDRIVEN_HS or IDRIVEN_LS = 0101b		700
			IDRIVEN_HS or IDRIVEN_LS = 0110b		800
			IDRIVEN_HS or IDRIVEN_LS = 0111b		900
			IDRIVEN_HS or IDRIVEN_LS = 1000b		1100
			IDRIVEN_HS or IDRIVEN_LS = 1001b		1200
			IDRIVEN_HS or IDRIVEN_LS = 1010b		1300
			IDRIVEN_HS or IDRIVEN_LS = 1011b		1400
			IDRIVEN_HS or IDRIVEN_LS = 1100b		1700
			IDRIVEN_HS or IDRIVEN_LS = 1101b		1800
			IDRIVEN_HS or IDRIVEN_LS = 1110b		1900
			IDRIVEN_HS or IDRIVEN_LS = 1111b		2000
		H/W Device	IDRIVE = Tied to GND		100
			IDRIVE = 18 kΩ ± 5% tied to GND		200
			IDRIVE = 75 kΩ ± 5% tied to GND		300
			IDRIVE = Hi-Z		600
			IDRIVE = 75 kΩ ± 5% tied to DVDD		900
			IDRIVE = 18 kΩ ± 5% tied to DVDD		1400
			IDRIVE = Tied to DVDD		2000
I_HOLD	Gate holding current		Source current after t_DRIVE		50		mA
I_HOLD	Gate holding current		Sink current after t_DRIVE		100		mA
I_STRONG	Gate strong pulldown current		GHx to SHx and GLx to SPx/SLx		2		A
R_OFF	Gate hold off resistor		GHx to SHx and GLx to SPx/SLx		150		kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
G_CSA	Amplifier gain	SPI Device	CSA_GAIN = 00b	4.85	5	5.15	V/V
			CSA_GAIN = 01b	9.7	10	10.3
			CSA_GAIN = 10b	19.4	20	20.6
			CSA_GAIN = 11b	38.8	40	41.2
		H/W Device	GAIN = Tied to GND	4.85	5	5.15
			GAIN = 47 kΩ ± 5% tied to GND	9.7	10	10.3
			GAIN = Hi-Z	19.4	20	20.6
			GAIN = Tied to DVDD	38.8	40	41.2
t_SET	Settling time to ±1%		V_{O_STEP} = 0.5 V, G_CSA = 5 V/V		250		ns
			V_{O_STEP} = 0.5 V, G_CSA = 10 V/V		500
			V_{O_STEP} = 0.5 V, G_VSA = 20 V/V		1000
			V_{O_STEP} = 0.5 V, G_CSA = 40 V/V		2000
V_COM	Common mode input range			–0.15		0.15	V
V_DIFF	Differential mode input range			–0.3		0.3	V
V_OFF	Input offset error		V_SP = V_SN = 0 V	–3		3	mV
V_DRIFT	Drift offset		V_SP = V_SN = 0 V		10		µV/°C
V_LINEAR	SOx output voltage linear range			0.25		V_VREF – 0.25	V
V_BIAS	SOx output voltage bias	SPI Device	V_SP = V_SN = 0 V, VREF_DIV = 0b		V_VREF – 0.3		V
		SPI Device	V_SP = V_SN = 0 V, VREF_DIV = 1b		V_VREF / 2
		H/W Device	V_SP = V_SN = 0 V		V_VREF / 2
I_BIAS	SPx/SNx input bias current					250	µA
V_SLEW	SOx output slew rate		60-pF load		10		V/µs
I_VREF	VREF input current		V_VREF = 5 V		1.5	2.5	mA
UGB	Unity gain bandwidth		DRV835x: 60-pF load		10		MHz
UGB	Unity gain bandwidth		DRV835xR: 60-pF load		1		MHz
PROTECTION CIRCUITS
V_{VM_UV}	VM undervoltage lockout		DRV835x: VM falling, UVLO report	8.0	8.3	8.8	V
			DRV835x: VM rising, UVLO recovery	8.2	8.5	9.0
			DRV835xR: VM falling, UVLO report	8.0	8.3	8.6
			DRV835xR: VM rising, UVLO recovery	8.2	8.5	8.8
V_{VM_UVH}	VM undervoltage hysteresis		Rising to falling threshold		200		mV
t_{VM_UVD}	VM undervoltage deglitch time		VM falling, UVLO report		10		µs
V_{VDR_UV}	VDRAIN undervoltage lockout		DRV835x: VDRAIN falling, UVLO report	6.1	6.4	6.8	V
			DRV835x: VDRAIN rising, UVLO recovery	6.3	6.6	7.0
			DRV835xR: VDRAIN falling, UVLO report	6.1	6.4	6.7
			DRV835xR: VDRAIN rising, UVLO recovery	6.3	6.6	6.9
V_{VDR_UVH}	VDRAIN undervoltage hysteresis		Rising to falling threshold		200		mV
t_{VDR_UVD}	VDRAIN undervoltage deglitch time		VDRAIN falling, UVLO report		10		µs
V_{VCP_UV}	VCP charge pump undervoltage lockout		VCP falling, GDUV report		V_DRAIN + 5		V
V_{VGLS_UV}	VGLS low-side regulator undervoltage lockout		VGLS falling, GDUV report		4.25		V
V_{GS_CLAMP}	High-side gate clamp		Positive clamping voltage	12.5	13.5	16	V
V_{GS_CLAMP}	High-side gate clamp		Negative clamping voltage		–0.7		V
V_{VDS_OCP}	V_DS overcurrent trip voltage	SPI Device	DRV835x: VDS_LVL = 0000b	0.041	0.06	0.072	V
			DRV835x: VDS_LVL = 0001b	0.051	0.07	0.084
			DRV835x: VDS_LVL = 0010b	0.061	0.08	0.096
			DRV835x: VDS_LVL = 0011b	0.071	0.09	0.108
			DRV835x: VDS_LVL = 0100b	0.081	0.1	0.115
			DRV835xR: VDS_LVL = 0000b	0.048	0.06	0.072
			DRV835xR: VDS_LVL = 0001b	0.056	0.07	0.084
			DRV835xR: VDS_LVL = 0010b	0.064	0.08	0.096
			DRV835xR: VDS_LVL = 0011b	0.072	0.09	0.108
			DRV835xR: VDS_LVL = 0100b	0.085	0.1	0.115
			VDS_LVL = 0101b	0.18	0.2	0.22
			VDS_LVL = 0110b	0.27	0.3	0.33
			VDS_LVL = 0111b	0.36	0.4	0.44
			VDS_LVL = 1000b	0.45	0.5	0.55
			VDS_LVL = 1001b	0.54	0.6	0.66
			VDS_LVL = 1010b	0.63	0.7	0.77
			VDS_LVL = 1011b	0.72	0.8	0.88
			VDS_LVL = 1100b	0.81	0.9	0.99
			VDS_LVL = 1101b	0.9	1.0	1.1
			VDS_LVL = 1110b	1.35	1.5	1.65
			VDS_LVL = 1111b	1.8	2	2.2
		H/W Device	DRV835x: VDS = Tied to GND	0.041	0.06	0.072	V
			DRV835x: VDS = 18 kΩ ± 5% tied to GND	0.081	0.1	0.115
			DRV835xR: VDS = Tied to GND	0.048	0.06	0.072
			DRV835xR: VDS = 18 kΩ ± 5% tied to GND	0.085	0.1	0.115
			VDS = 75 kΩ ± 5% tied to GND	0.18	0.2	0.22
			VDS = Hi-Z	0.36	0.4	0.44
			VDS = 75 kΩ ± 5% tied to DVDD	0.63	0.7	0.77
			VDS = 18 kΩ ± 5% tied to DVDD	0.9	1	1.1
			VDS = Tied to DVDD	Disabled
t_{OCP_DEG}	V_DS and V_SENSE overcurrent deglitch time	SPI Device	OCP_DEG = 00b		1		µs
			OCP_DEG = 01b		2
			OCP_DEG = 10b		4
			OCP_DEG = 11b		8
		H/W Device			4
V_{SEN_OCP}	V_SENSE overcurrent trip voltage	SPI Device	SEN_LVL = 00b		0.25		V
			SEN_LVL = 01b		0.5
			SEN_LVL = 10b		0.75
			SEN_LVL = 11b		1
		H/W Device			1
t_RETRY	Overcurrent retry time	SPI Device	TRETRY = 0b		8		ms
		SPI Device	TRETRY = 1b		50		μs
		H/W Device			8		ms
T_OTW	Thermal warning temperature		Die temperature, T_J	130	150	170	°C
T_OTSD	Thermal shutdown temperature		Die temperature, T_J	150	170	190	°C
T_HYS	Thermal hysteresis		Die temperature, T_J		20		°C
BUCK REGULATOR VCC
V_{VCC_REG}	VCC regulator voltage			6.6	7	7.4	V
V_{VCC_REG}	VCC regulator voltage		V_VIN = 6 to 8.5 V		100		mV
V_{VCC_BYT}	VCC bypass threshold		V_VIN increasing		8.5		V
V_{VCC_BYH}	VCC bypass hysteresis				300		mV
V_{VCC_OUT}	VCC output impedance		V_VIN = 6 V		100		Ω
			V_VIN = 10 V		8.8		Ω
			V_VIN = 48 V		0.8		Ω
V_{VCC_LIM}	VCC current limit				9.2		mA
V_{VCC_UV}	VCC undervoltage lockout				5.3		V
V_{VCC_UVH}	VCC undervoltage lockout hysteresis				190		mV
V_{VCC_UVFD}	VCC filter delay				3		μs
I_{IN_OP}	IIN operating current		FB = 3 V		550	750	μA
I_{IN_OP}	IIN shutdown current		RT/SD = 0 V		110	176	μA
BUCK REGULATOR SWITCHING
R_DS(on)	Buck switch R_DS(on)		I_TEST = 200 mA		1.25	2.57	Ω
V_{GATE_UV}	Gate drive undervoltage lockout		V_BST - V_SW rising	2.8	3.8	4.8	V
V_{GATE_UVH}	Gate drive undervoltage lockout hysteresis				490		mV
V_SWITCH	Pre-charge switch voltage		At 1 mA		0.8		V
t_ON	Pre-charge switch on-time				150		ns
BUCK REGULATOR CURRENT LIMIT
I_LIMIT	Current limit threshold			0.41	0.51	0.61	A
t_LIM	Current limit response time		I_SW overdrive = 0.1 A, time to switch off		350		ns
t_OFF1	Off time generator		FB = 0 V, RCL = 100 kΩ		35		μs
t_OFF2	Off time generator		FB = 2.3 V, RCL = 100 kΩ		2.56		μs
BUCK REGULATOR ON TIME GENERATOR
t_ON1	Ton 1		V_VIN = 10 V, RON = 200 kΩ	2.15	2.77	3.5	μs
t_ON2	Ton 2		V_VIN = 95 V, RON = 200 kΩ	200	300	420	μs
V_SDT	Remote shutdown threshold		Rising	0.4	0.7	1.05	V
V_SDH	Remote shutdown hysteresis				35		mV
BUCK REGULATOR MINIMUM OFF TIME
t_{OFF_MIN}	Minimum off time		FB = 0 V		300		ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
V_FB	FB reference threshold		Internal reference, trip point for switch on	2.445	2.5	2.55	V
V_{FB_OV}	FB overvoltage threshold		Trip point for switch off		2.875		V
I_{FB_BIAS}	FB bias current				100		μA
BUCK REGULATOR THERMAL SHUTDOWN
T_SD	Thermal shutdown threshold				165		°C
T_SDH	Thermal shutdown hysteresis				25		°C