ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Three Phase Smart Gate Drivers
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4 Low-Side Current Sense Amplifiers (DRV8323 and DRV8323R Only)
- 8.3.5 Step-Down Buck Regulator
- 8.3.6 Gate Driver Protective Circuits
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- Table 1. DRV832xS and DRV832xRS Register Map
- 8.6.1 Status Registers
- 8.6.2 Control Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Primary Application
- 9.2.1.1 Design Requirements
- 9.2.1.2 Detailed Design Procedure
- 9.2.1.3 Application Curves
- 9.2.2 Alternative Application
- 9.2.1
Primary Application
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three current sense amplifiers (DRV8323 and DRV8323R), the low-side VDS monitors measure the voltage between the SHx and SPx pins. If the current sense amplifier is unused, tie the SP pins to the common ground point of the external half-bridges. On device options without the current sense amplifiers (DRV8320 and DRV8320R) the low-side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the reference point of the low-side VDS monitor can be changed between the SPx and SNx pins if desired with the LS_REF register setting.
The VVDS_OCP threshold is programmable from 0.06 V to 1.88 V. For additional information on the VDS monitor levels, see the Register Maps section for SPI devices and in the Pin Diagrams section hardware interface device.
Figure 28. DRV8320 and DRV8320R VDS Monitors 
Figure 29. DRV8323 and DRV8323R VDS Monitors