ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Three Phase Smart Gate Drivers
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4 Low-Side Current Sense Amplifiers (DRV8323 and DRV8323R Only)
- 8.3.5 Step-Down Buck Regulator
- 8.3.6 Gate Driver Protective Circuits
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- Table 1. DRV832xS and DRV832xRS Register Map
- 8.6.1 Status Registers
- 8.6.2 Control Registers
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Primary Application
- 9.2.1.1 Design Requirements
- 9.2.1.2 Detailed Design Procedure
- 9.2.1.3 Application Curves
- 9.2.2 Alternative Application
- 9.2.1
Primary Application
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTA|40
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.6 SPI Timing Requirements(1)
at TA = –40°C to +125°C, VVM = 6 to 60 V (unless otherwise noted)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| SPI (nSCS, SCLK, SDI, SDO) | ||||||
| tREADY | SPI ready after enable | VM > UVLO, ENABLE = 3.3 V | 1 | ms | ||
| tCLK | SCLK minimum period | 100 | ns | |||
| tCLKH | SCLK minimum high time | 50 | ns | |||
| tCLKL | SCLK minimum low time | 50 | ns | |||
| tSU_SDI | SDI input data setup time | 20 | ns | |||
| tH_SDI | SDI input data hold time | 30 | ns | |||
| tD_SDO | SDO output data delay time | SCLK high to SDO valid | 30 | ns | ||
| tSU_nSCS | nSCS input setup time | 50 | ns | |||
| tH_nSCS | nSCS input hold time | 50 | ns | |||
| tHI_nSCS | nSCS minimum high time before active low | 400 | ns | |||
| tDIS_nSCS | nSCS disable time | nSCS high to SDO high impedance | 10 | ns | ||
(1) Specified by design and characterization data
