ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current sense resistor with the SP pin. If at any time the voltage on the SP input of the CSA exceeds the VSEN_OCP threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done according to the OCP_MODE bit. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 4-ms automatic retry. On SPI devices, the VSENSE threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and VSENSE disabled.