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ZHCSG01C February 2017 – August 2018 DRV8320 , DRV8320R , DRV8323 , DRV8323R

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHA|40
- MPQF135D

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.5 Electrical Characteristics

at T_A = –40°C to +125°C, V_VM = 6 to 60 V (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLIES (DVDD, VCP, VM)
I_VM	VM operating supply current		V_VM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V		10.5	14	mA
I_VMQ	VM sleep mode supply current		ENABLE = 0 V, V_VM = 24 V, T_A = 25°C		12	20	µA
I_VMQ	VM sleep mode supply current		ENABLE = 0 V, V_VM = 24 V, T_A = 125°C⁽¹⁾			50	µA
t_RST⁽¹⁾	Reset pulse time		ENABLE = 0 V period to reset faults	8		40	µs
t_WAKE	Turnon time		V_VM > V_UVLO, ENABLE = 3.3 V to outputs ready			1	ms
t_SLEEP	Turnoff time		ENABLE = 0 V to device sleep mode			1	ms
V_DVDD	DVDD regulator voltage		I_DVDD = 0 to 30 mA	3	3.3	3.6	V
V_VCP	VCP operating voltage with respect to VM		V_VM = 13 V, I_VCP = 0 to 25 mA	8.4	11	12.5	V
			V_VM = 10 V, I_VCP = 0 to 20 mA	6.3	9	10
			V_VM = 8 V, I_VCP = 0 to 15 mA	5.4	7	8
			V_VM = 6 V, I_VCP = 0 to 10 mA	4	5	6
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI)
V_IL	Input logic low voltage			0		0.8	V
V_IH	Input logic high voltage			1.5		5.5	V
V_HYS	Input logic hysteresis				100		mV
I_IL	Input logic low current		V_VIN = 0 V	–5		5	µA
I_IH	Input logic high current		V_VIN = 5 V		50	70	µA
R_PD	Pulldown resistance		To AGND		100		kΩ
t_PD	Propagation delay		INHx/INLx transition to GHx/GLx transition		150		ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
V_I1	Input mode 1 voltage		Tied to AGND		0		V
V_I2	Input mode 2 voltage		45 kΩ ± 5% to tied AGND		1.2		V
V_I3	Input mode 3 voltage		Hi-Z		2		V
V_I4	Input mode 4 voltage		Tied to DVDD		3.3		V
R_PU	Pullup resistance		Internal pullup to DVDD		50		kΩ
R_PD	Pulldown resistance		Internal pulldown to AGND		84		kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
V_I1	Input mode 1 voltage		Tied to AGND		0		V
V_I2	Input mode 2 voltage		18 kΩ ± 5% tied to AGND		0.5		V
V_I3	Input mode 3 voltage		75 kΩ ± 5% tied to AGND		1.1		V
V_I4	Input mode 4 voltage		Hi-Z		1.65		V
V_I5	Input mode 5 voltage		75 kΩ ± 5% tied to DVDD		2.2		V
V_I6	Input mode 6 voltage		18 kΩ ± 5% tied to DVDD		2.8		V
V_I7	Input mode 7 voltage		Tied to DVDD		3.3		V
R_PU	Pullup resistance		Internal pullup to DVDD		73		kΩ
R_PD	Pulldown resistance		Internal pulldown to AGND		73		kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
V_OL	Output logic low voltage		I_O = 5 mA			0.1	V
I_OZ	Output high impedance leakage		V_O = 5 V	–2		2	µA
GATE DRIVERS (GHx, GLx)
V_GSH⁽¹⁾	High-side gate drive voltage with respect to SHx		V_VM = 13 V, I_VCP = 0 to 25 mA	8.4	11	12.5	V
			V_VM = 10 , I_VCP = 0 to 20 mA	6.3	9	10
			V_VM = 8 V, I_VCP = 0 to 15 mA	5.4	7	8
			V_VM = 6 V, I_VCP = 0 to 10 mA	4	5	6
V_GSL⁽¹⁾	Low-side gate drive voltage with respect to PGND		V_VM = 12 V, I_VGLS = 0 to 25 mA	9	11	12	V
			V_VM = 10 V, I_VGLS = 0 to 20 mA	7.5	9	10
			V_VM = 8 V, I_VGLS = 0 to 15 mA	5.5	7	8
			V_VM = 6 V, I_VGLS = 0 to 10 mA	4	5	6
t_DEAD	Gate drive dead time	SPI Device	DEAD_TIME = 00b		50		ns
			DEAD_TIME = 01b		100
			DEAD_TIME = 10b		200
			DEAD_TIME = 11b		400
		H/W Device			100
t_DRIVE	Peak current gate drive time	SPI Device	TDRIVE = 00b		500		ns
			TDRIVE = 01b		1000
			TDRIVE = 10b		2000
			TDRIVE = 11b		4000
		H/W Device			4000
I_DRIVEP	Peak source gate current	SPI Device	IDRIVEP_HS or IDRIVEP_LS = 0000b		10		mA
			IDRIVEP_HS or IDRIVEP_LS = 0001b		30
			IDRIVEP_HS or IDRIVEP_LS = 0010b		60
			IDRIVEP_HS or IDRIVEP_LS = 0011b		80
			IDRIVEP_HS or IDRIVEP_LS = 0100b		120
			IDRIVEP_HS or IDRIVEP_LS = 0101b		140
			IDRIVEP_HS or IDRIVEP_LS = 0110b		170
			IDRIVEP_HS or IDRIVEP_LS = 0111b		190
			IDRIVEP_HS or IDRIVEP_LS = 1000b		260
			IDRIVEP_HS or IDRIVEP_LS = 1001b		330
			IDRIVEP_HS or IDRIVEP_LS = 1010b		370
			IDRIVEP_HS or IDRIVEP_LS = 1011b		440
			IDRIVEP_HS or IDRIVEP_LS = 1100b		570
			IDRIVEP_HS or IDRIVEP_LS = 1101b		680
			IDRIVEP_HS or IDRIVEP_LS = 1110b		820
			IDRIVEP_HS or IDRIVEP_LS = 1111b		1000
		H/W Device	IDRIVE = Tied to AGND		10
			IDRIVE = 18 kΩ ± 5% tied to AGND		30
			IDRIVE = 75 kΩ ± 5% tied to AGND		60
			IDRIVE = Hi-Z		120
			IDRIVE = 75 kΩ ± 5% tied to DVDD		260
			IDRIVE = 18 kΩ ± 5% tied to DVDD		570
			IDRIVE = Tied to DVDD		1000
I_DRIVEN	Peak sink gate current	SPI Device	IDRIVEN_HS or IDRIVEN_LS = 0000b		20		mA
			IDRIVEN_HS or IDRIVEN_LS = 0001b		60
			IDRIVEN_HS or IDRIVEN_LS = 0010b		120
			IDRIVEN_HS or IDRIVEN_LS = 0011b		160
			IDRIVEN_HS or IDRIVEN_LS = 0100b		240
			IDRIVEN_HS or IDRIVEN_LS = 0101b		280
			IDRIVEN_HS or IDRIVEN_LS = 0110b		340
			IDRIVEN_HS or IDRIVEN_LS = 0111b		380
			IDRIVEN_HS or IDRIVEN_LS = 1000b		520
			IDRIVEN_HS or IDRIVEN_LS = 1001b		660
			IDRIVEN_HS or IDRIVEN_LS = 1010b		740
			IDRIVEN_HS or IDRIVEN_LS = 1011b		880
			IDRIVEN_HS or IDRIVEN_LS = 1100b		1140
			IDRIVEN_HS or IDRIVEN_LS = 1101b		1360
			IDRIVEN_HS or IDRIVEN_LS = 1110b		1640
			IDRIVEN_HS or IDRIVEN_LS = 1111b		2000
		H/W Device	IDRIVE = Tied to AGND		20
			IDRIVE = 18 kΩ ± 5% tied to AGND		60
			IDRIVE = 75 kΩ ± 5% tied to AGND		120
			IDRIVE = Hi-Z		240
			IDRIVE = 75 kΩ ± 5% tied to DVDD		520
			IDRIVE = 18 kΩ ± 5% tied to DVDD		1140
			IDRIVE = Tied to DVDD		2000
I_HOLD	Gate holding current		Source current after t_DRIVE		10		mA
I_HOLD	Gate holding current		Sink current after t_DRIVE		50		mA
I_STRONG	Gate strong pulldown current		GHx to SHx and GLx to PGND		2		A
R_OFF	Gate hold off resistor		GHx to SHx and GLx to PGND		150		kΩ
CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF)
G_CSA	Amplifier gain	SPI Device	CSA_GAIN = 00b	4.85	5	5.15	V/V
			CSA_GAIN = 01b	9.7	10	10.3
			CSA_GAIN = 10b	19.4	20	20.6
			CSA_GAIN = 11b	38.8	40	41.2
		H/W Device	GAIN = Tied to AGND	4.85	5	5.15
			GAIN = 47 kΩ ± 5% tied to AGND	9.7	10	10.3
			GAIN = Hi-Z	19.4	20	20.6
			GAIN = Tied to DVDD	38.8	40	41.2
t_SET⁽¹⁾	Settling time to ±1%		V_{O_STEP} = 0.5 V, G_CSA = 5 V/V		150		ns
			V_{O_STEP} = 0.5 V, G_CSA = 10 V/V		300
			V_{O_STEP} = 0.5 V, G_VSA = 20 V/V		600
			V_{O_STEP} = 0.5 V, G_CSA = 40 V/V		1200
V_COM	Common mode input range			–0.15		0.15	V
V_DIFF	Differential mode input range			–0.3		0.3	V
V_OFF	Input offset error		V_SP = V_SN = 0 V, CAL = 3.3 V, VREF = 3.3 V	–4		4	mV
V_DRIFT⁽¹⁾	Drift offset		V_SP = V_SN = 0 V		10		µV/°C
V_LINEAR	SOx output voltage linear range			0.25		V_VREF – 0.25	V
V_BIAS	SOx output voltage bias	SPI Device	V_SP = V_SN = 0 V, CAL = 3.3 V, VREF_DIV = 0b	V_VREF – 0.3			V
		SPI Device	V_SP = V_SN = 0 V, CAL = 3.3 V, VREF_DIV = 1b	V_VREF / 2
		H/W Device	V_SP = V_SN = 0 V, CAL = 3.3 V	V_VREF / 2
I_BIAS	SPx/SNx input bias current		VREF_DIV = 1b			100	µA
V_SLEW⁽¹⁾	SOx output slew rate		60-pF load		10		V/µs
I_VREF	VREF input current		V_VREF = 5 V		2	3	mA
UGB⁽¹⁾	Unity gain bandwidth		60-pF load		1		MHz
PROTECTION CIRCUITS
V_UVLO	VM undervoltage lockout		VM falling, UVLO report	5.4	5.6	5.8	V
V_UVLO	VM undervoltage lockout		VM rising, UVLO recovery	5.6	5.8	6	V
V_{UVLO_HYS}	VM undervoltage hysteresis		Rising to falling threshold		200		mV
t_{UVLO_DEG}	VM undervoltage deglitch time		VM falling, UVLO report		10		µs
V_CPUV	Charge pump undervoltage lockout		VCP falling, CPUV report	V_VM + 2.8			V
V_{GS_CLAMP}	High-side gate clamp		Positive clamping voltage	15	16.5	18	V
V_{GS_CLAMP}	High-side gate clamp		Negative clamping voltage		–0.7		V
V_{VDS_OCP}	V_DS overcurrent trip voltage	SPI Device	VDS_LVL = 0000b		0.06		V
			VDS_LVL = 0001b		0.13
			VDS_LVL = 0010b		0.2
			VDS_LVL = 0011b		0.26
			VDS_LVL = 0100b		0.31
			VDS_LVL = 0101b		0.45
			VDS_LVL = 0110b		0.53
			VDS_LVL = 0111b		0.6
			VDS_LVL = 1000b		0.68
			VDS_LVL = 1001b		0.75
			VDS_LVL = 1010b		0.94
			VDS_LVL = 1011b		1.13
			VDS_LVL = 1100b		1.3
			VDS_LVL = 1101b		1.5
			VDS_LVL = 1110b		1.7
			VDS_LVL = 1111b		1.88
		H/W Device	VDS = Tied to AGND		0.06
			VDS = 18 kΩ ± 5% tied to AGND		0.13
			VDS = 75 kΩ ± 5% tied to AGND		0.26
			VDS = Hi-Z		0.6
			VDS = 75 kΩ ± 5% tied to DVDD		1.13
			VDS = 18 kΩ ± 5% tied to DVDD		1.88
			VDS = Tied to DVDD	Disabled
t_{OCP_DEG}	V_DS and V_SENSE overcurrent deglitch time	SPI Device	OCP_DEG = 00b		2		µs
			OCP_DEG = 01b		4
			OCP_DEG = 10b		6
			OCP_DEG = 11b		8
		H/W Device			4
V_{SEN_OCP}	V_SENSE overcurrent trip voltage	SPI Device	SEN_LVL = 00b		0.25		V
			SEN_LVL = 01b		0.5
			SEN_LVL = 10b		0.75
			SEN_LVL = 11b		1
		H/W Device			1
t_RETRY	Overcurrent retry time	SPI Device	TRETRY = 0b		4		ms
		SPI Device	TRETRY = 1b		50		μs
		H/W Device			4		ms
T_OTW⁽¹⁾	Thermal warning temperature		Die temperature, T_J	130	150	165	°C
T_OTSD⁽¹⁾	Thermal shutdown temperature		Die temperature, T_J	150	170	185	°C
T_HYS⁽¹⁾	Thermal hysteresis		Die temperature, T_J		20		°C
BUCK REGULATOR SUPPLY (VIN)
I_nSHDN	Shutdown supply current		V_nSHDN = 0 V		1	3	µA
I_Q	Operating quiescent current		V_VIN = 12 V, no load; not switching		28		µA
V_{VIN_UVLO}	VIN undervoltage lockout threshold		VIN Rising			4	V
V_{VIN_UVLO}	VIN undervoltage lockout threshold		VIN Falling	3			V
BUCK REGULATOR SHUTDOWN (nSHDN)
V_{nSHDN_TH}	Rising nSHDN threshold			1.05	1.25	1.38	V
I_nSHDN	Input current		V_nSHDN = 2.3 V		–4.2		µA
I_nSHDN	Input current		V_nSHDN = 0.9 V		–1		µA
I_{nSHDN_HYS}	Hysteresis current				–3		µA
BUCK REGULATOR HIGH-SIDE MOSFET
R_{DS_ON}	MOSFET on resistance		V_VIN = 12 V, V_CB to V_SW = 5.8 V, T_A = 25°C		900		mΩ
BUCK REGULATOR VOLTAGE REFERENCE (FB)
V_FB	Feedback voltage			0.747	0.765	0.782	V
BUCK REGULATOR CURRENT LIMIT
I_LIMIT	Peak current limit		V_VIN = 12 V, T_A = 25°C		1200		mA
I_LIMIT	Peak current limit					1700	mA
BUCK REGULATOR SWITCHING (SW)
f_SW	Switching frequency			595	700	805	kHz
D_MAX	Maximum duty cycle				96%
BUCK REGULATOR THERMAL SHUTDOWN
T_SHDN⁽¹⁾	Thermal shutdown threshold				170		°C
T_HYS⁽¹⁾	Thermal shutdown hysteresis				10		°C

(1) Specified by design and characterization data