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ZHCSRG7 January 2023 DRV2901

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDV|44
- MPDS169G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDV|44
- PPTD081B

訂購信息

6.5 Electrical Characteristics

R_L= 6 ?, F_PWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.

PARAMETER		TEST CONDITIONS	DRV2900			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Internal Voltage Regulator and Current Consumption
VREG	Voltage regulator, only used as a reference node	VDD = 12 V	2.95	3.3	3.65	V
IVDD	VDD supply current	Operating, 50% duty cycle		10		mA
IVDD	VDD supply current	Idle, reset mode		6		mA
IGVDD_X	Gate supply current per half-bridge	50% duty cycle		8		mA
IGVDD_X	Gate supply current per half-bridge	Reset mode		0.3		mA
IPVDD_X	Half-bridge idle current	50% duty cycle, without output filter or load		15		mA
IPVDD_X	Half-bridge idle current	Reset mode, no switching		500		μA
Output Stage MOSFETs
R_DSon,LS	Drain-to-source resistance, LS	T_J = 25°C, includes metallization resistance, GVDD = 12 V		90		m?
R_DSon,HS	Drain-to-source resistance, HS	T_J = 25°C, includes metallization resistance, GVDD = 12 V		90		m?
I/O Protection
V_uvp,G	Undervoltage protection limit, GVDD_X			8.5		V
V_uvp,hyst ⁽¹⁾				400		mV
OTW⁽¹⁾	Overtemperature warning		115	125	135	°C
OTW_HYST ⁽¹⁾	Temperature drop needed below OTW temp. for OTW to be inactive after the OTW event			25		°C
OTE⁽¹⁾	Overtemperature error		145	155	165	°C
OTE-OTW_differential ⁽¹⁾	OTE-OTW differential			25		°C
OTE_HYST ⁽¹⁾	A reset needs to occur for SD for be released following an OTE event.			25		°C
OLPC	Overload protection counter	F_PWM = 384 kHz		1.3		ms
I_OC	Overcurrent limit protection	Resistor—programmable, nominal, R_OCP = 22 k?		12		A
I_OCT	Overcurrent response time	Time from application of short condition to Hi-Z of affected 1/2 bridge		250		ns
R_OCP	OC programming resistor range	Resistor tolerance = 5%	22		69	k?
R_PD	Internal pulldown resistor at the output of each half-bridge	Connected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode		1.0		k?
Static Digital Specifications
V_IH	High-level input voltage	PWM_A, PWM_B, RESET_AB	2			V
V_IL	Low-level input voltage	PWM_A, PWM_B, RESET_AB			0.8	V
Leakage	Input leakage current		-100		100	μA
OTW/SHUTDOWN (SD)
R_{INT_PU}	Internal pullup resistance, OTW to VREG, SD to VREG		20	26	35	k?
V_OH	High-level output voltage	Internal pullup resistor	2.95	3.3	3.65	V
V_OH	High-level output voltage	External pullup of 4.7 k? to 5 V	4.5		5	V
V_OL	Low-level output voltage	I_O = 4 mA		0.2	0.4	V
FANOUT	Device fanout OTW, SD	No external pullup		30		Devices

(1) Specified by design