ZHCSEJ7B October 2015 – April 2018 DRV2605L-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Support for ERM and LRA Actuators
- 7.3.2 Smart-Loop Architecture
- 7.3.3 Open-Loop Operation for LRA
- 7.3.4 Open-Loop Operation for ERM
- 7.3.5 Flexible Front-End Interface
- 7.3.6 Edge Rate Control
- 7.3.7 Constant Vibration Strength
- 7.3.8 Battery Voltage Reporting
- 7.3.9 Low-Power Standby
- 7.3.10 I2C Watchdog Timer
- 7.3.11 Device Protection
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Auto-Resonance Engine Programming for the LRA
- 7.5.2 Automatic-Level Calibration Programming
- 7.5.3 I2C Interface
- 7.5.4 Programming for Open-Loop Operation
- 7.5.5 Programming for Closed-Loop Operation
- 7.5.6 Auto Calibration Procedure
- 7.5.7 Waveform Playback Programming
- 7.6
Register Map
- 7.6.1 Status (Address: 0x00)
- 7.6.2 Mode (Address: 0x01)
- 7.6.3 Real-Time Playback Input (Address: 0x02)
- 7.6.4 (Address: 0x03)
- 7.6.5 Waveform Sequencer (Address: 0x04 to 0x0B)
- 7.6.6 GO (Address: 0x0C)
- 7.6.7 Overdrive Time Offset (Address: 0x0D)
- 7.6.8 Sustain Time Offset, Positive (Address: 0x0E)
- 7.6.9 Sustain Time Offset, Negative (Address: 0x0F)
- 7.6.10 Brake Time Offset (Address: 0x10)
- 7.6.11 Audio-to-Vibe Control (Address: 0x11)
- 7.6.12 Audio-to-Vibe Minimum Input Level (Address: 0x12)
- 7.6.13 Audio-to-Vibe Maximum Input Level (Address: 0x13)
- 7.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14)
- 7.6.15 Audio-to-Vibe Maximum Output Drive (Address: 0x15)
- 7.6.16 Rated Voltage (Address: 0x16)
- 7.6.17 Overdrive Clamp Voltage (Address: 0x17)
- 7.6.18 Auto-Calibration Compensation Result (Address: 0x18)
- 7.6.19 Auto-Calibration Back-EMF Result (Address: 0x19)
- 7.6.20 Feedback Control (Address: 0x1A)
- 7.6.21 Control1 (Address: 0x1B)
- 7.6.22 Control2 (Address: 0x1C)
- 7.6.23 Control3 (Address: 0x1D)
- 7.6.24 Control4 (Address: 0x1E)
- 7.6.25 Control5 (Address: 0x1F)
- 7.6.26 LRA Open Loop Period (Address: 0x20)
- 7.6.27 V(BAT) Voltage Monitor (Address: 0x21)
- 7.6.28 LRA Resonance Period (Address: 0x22)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.5.3.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 19 shows a typical sequence. The master device generates the 7-bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection.
The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word transfers, the master generates a stop condition to release the bus. Figure 19 shows a generic data-transfer sequence.
Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors with values between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2605L-Q1 supply voltage, VDD.
NOTE
The DRV2605L-Q1 slave address is 0x5A (7-bit), or 1011010 in binary.
Figure 19. Typical I2C Sequence The DRV2605L-Q1 device operates as an I2C-slave 1.8-V logic thresholds, but can operate up to the VDD voltage. The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5 (8-bit) for reading.