ZHCSEJ7B October 2015 – April 2018 DRV2605L-Q1
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STARTUP_BOOST | Reserved | AC_COUPLE | DRIVE_TIME[4:0] | ||||
| R/W-1 | R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-1 | R/W-1 | |
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION | ||
|---|---|---|---|---|---|---|
| 7 | STARTUP_BOOST | R/W | 1 |
This bit applies higher loop gain during overdrive to enhance actuator transient response. |
||
| 6 | Reserved | |||||
| 5 | AC_COUPLE | R/W | 0 |
This bit applies a 0.9-V common mode voltage to the IN/TRIG pin when an AC-coupling capacitor is used. This bit is only useful for analog input mode. This bit should not be asserted for PWM mode or external trigger mode.
0: Common-mode drive disabled for DC-coupling or digital inputs modes 1: Common-mode drive enabled for AC coupling |
||
| 4-0 | DRIVE_TIME[4:0] | R/W | 0x13 |
LRA Mode: Sets initial guess for LRA drive-time in LRA mode. Drive time is automatically adjusted for optimum drive in real time; however, this register should be optimized for the approximate LRA frequency. If the bit is set too low, it can affect the actuator startup time. If the bit is set too high, it can cause instability. Optimum drive time (ms) ≈ 0.5 × LRA Period Drive time (ms) = DRIVE_TIME[4:0] × 0.1 ms + 0.5 ms ERM Mode: Sets the sample rate for the back-EMF detection. Lower drive times cause higher peak-to-average ratios in the output signal, requiring more supply headroom. Higher drive times cause the feedback to react at a slower rate. Drive Time (ms) = DRIVE_TIME[4:0] × 0.2 ms + 1 ms |
||