ZHCSEJ7B October 2015 – April 2018 DRV2605L-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Support for ERM and LRA Actuators
- 7.3.2 Smart-Loop Architecture
- 7.3.3 Open-Loop Operation for LRA
- 7.3.4 Open-Loop Operation for ERM
- 7.3.5 Flexible Front-End Interface
- 7.3.6 Edge Rate Control
- 7.3.7 Constant Vibration Strength
- 7.3.8 Battery Voltage Reporting
- 7.3.9 Low-Power Standby
- 7.3.10 I2C Watchdog Timer
- 7.3.11 Device Protection
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Auto-Resonance Engine Programming for the LRA
- 7.5.2 Automatic-Level Calibration Programming
- 7.5.3 I2C Interface
- 7.5.4 Programming for Open-Loop Operation
- 7.5.5 Programming for Closed-Loop Operation
- 7.5.6 Auto Calibration Procedure
- 7.5.7 Waveform Playback Programming
- 7.6
Register Map
- 7.6.1 Status (Address: 0x00)
- 7.6.2 Mode (Address: 0x01)
- 7.6.3 Real-Time Playback Input (Address: 0x02)
- 7.6.4 (Address: 0x03)
- 7.6.5 Waveform Sequencer (Address: 0x04 to 0x0B)
- 7.6.6 GO (Address: 0x0C)
- 7.6.7 Overdrive Time Offset (Address: 0x0D)
- 7.6.8 Sustain Time Offset, Positive (Address: 0x0E)
- 7.6.9 Sustain Time Offset, Negative (Address: 0x0F)
- 7.6.10 Brake Time Offset (Address: 0x10)
- 7.6.11 Audio-to-Vibe Control (Address: 0x11)
- 7.6.12 Audio-to-Vibe Minimum Input Level (Address: 0x12)
- 7.6.13 Audio-to-Vibe Maximum Input Level (Address: 0x13)
- 7.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14)
- 7.6.15 Audio-to-Vibe Maximum Output Drive (Address: 0x15)
- 7.6.16 Rated Voltage (Address: 0x16)
- 7.6.17 Overdrive Clamp Voltage (Address: 0x17)
- 7.6.18 Auto-Calibration Compensation Result (Address: 0x18)
- 7.6.19 Auto-Calibration Back-EMF Result (Address: 0x19)
- 7.6.20 Feedback Control (Address: 0x1A)
- 7.6.21 Control1 (Address: 0x1B)
- 7.6.22 Control2 (Address: 0x1C)
- 7.6.23 Control3 (Address: 0x1D)
- 7.6.24 Control4 (Address: 0x1E)
- 7.6.25 Control5 (Address: 0x1F)
- 7.6.26 LRA Open Loop Period (Address: 0x20)
- 7.6.27 V(BAT) Voltage Monitor (Address: 0x21)
- 7.6.28 LRA Resonance Period (Address: 0x22)
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DGS|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.2.3 Automatic Switch to Open-Loop for LRA
In the event that an LRA produces a non-valid back-EMF signal, the DRV2605L-Q1 device automatically switches to open-loop operation and continues to deliver energy to the actuator in overdrive mode at a default and configurable frequency. Use Equation 1 to calculate the default frequency. If the LRA begins to produce a valid back-EMF signal, the auto-resonance engine automatically takes control and continues to track the resonant frequency in real time. When synchronized, the mode enjoys all of the benefits that the smart-loop architecture has to offer.
The DRV2605L-Q1 device offers an automatic transition to open-loop mode without the re-synchronization option. The feature is enabled by setting the LRA_AUTO_OPEN_LOOP bit in register 0x1F. The transition to open-loop mode only occurs when the driver fails to synchronize with the LRA. The AUTO_OL_CNT[1:0] bit in register 0x1F can be adjusted to set the amount of non-synchronized cycles allowed before the transition to the open-loop mode. Use Equation 2 to calculate the open-loop frequency. The open-loop mode does not receive benefits from the smart-loop architecture, such as automatic overdrive and braking.
