ZHCSDA7G July 2014 – February 2018 DRV10983
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Motor Parameters
- 8.4.2 Starting the Motor Under Different Initial Conditions
- 8.4.3 Motor Start Sequence
- 8.4.4 Start-Up Current Setting
- 8.4.5 Closed Loop
- 8.4.6 Current Limit
- 8.4.7 Lock Detect and Fault Handling
- 8.4.8 AVS Function
- 8.4.9 PWM Output
- 8.4.10 FG Customized Configuration
- 8.4.11
Diagnostics and Visibility
- 8.4.11.1 Motor Status Readback
- 8.4.11.2 Motor Speed Readback
- 8.4.11.3 Motor Electrical Period Readback
- 8.4.11.4 BEMF Constant Readback
- 8.4.11.5 Motor Estimated Position by IPD
- 8.4.11.6 Supply Voltage Readback
- 8.4.11.7 Speed Command Readback
- 8.4.11.8 Speed Command Buffer Readback
- 8.4.11.9 Fault Diagnostics
- 8.5 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.4.10.2 FG Open-Loop and Lock Behavior
Note that the FG output reflects the driving state of the motor. During normal closed loop behavior, the driving state and the actual state of the motor are synchronized. During open loop acceleration, however, this may not reflect the actual motor speed. During a locked motor condition, the FG output is driven high.
The DRV10983 provides three options for controlling the FG output during open loop as shown in Figure 37. The selection of these options is determined by the FGOLsel[1:0] setting.
- Option0: Open loop output FG based on driving frequency
- Option1: Open loop no FG output (keep high)
- Option2: FG output based on driving frequency at the first power-on start-up, and no FG output (keep high) for any subsequent restarts
