ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
| NO. | PARAMETER | DESCRIPTION | STANDARD MODE | FAST MODE | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||||
| 16 | tc(SCL) | Cycle time, SCL | 10 | 2.5 | µs | |||
| 17 | tsu(SCLH-SDAL) | Setup time, SCL high before SDA low (for a repeated START condition) | 4.7 | 0.6 | µs | |||
| 18 | th(SDAL-SCLL) | Hold time, SCL low after SDA low (for a START and a repeated START condition) | 4 | 0.6 | µs | |||
| 19 | tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | µs | |||
| 20 | tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | µs | |||
| 21 | tsu(SDAV-SCLH) | Setup time, SDA valid before SCL high | 250 | 100 | ns | |||
| 22 | th(SCLL-SDAV) | Hold time, SDA valid after SCL low (for I2C bus devices) | 0 | 3.45 | 0 | 0.9 | µs | |
| 23 | tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | µs | |||
| 24 | tr(SDA) | Rise time, SDA | 1000 | 20 + 0.1Cb(1)(3) | 300(3) | ns | ||
| 25 | tr(SCL) | Rise time, SCL | 1000 | 20 + 0.1Cb(1)(3) | 300(3) | ns | ||
| 26 | tf(SDA) | Fall time, SDA | 300 | 20 + 0.1Cb(1)(3) | 300(3) | ns | ||
| 27 | tf(SCL) | Fall time, SCL | 300 | 20 + 0.1Cb(1)(3) | 300(3) | ns | ||
| 28 | tsu(SCLH-SDAH) | Setup time, SCL high before SDA high (for STOP condition) | 4 | 0.6 | µs | |||
| 29 | Cp | Capacitance for each I2C pin | 10 | 10 | pF | |||
NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic-1.
Figure 7-24 I2C Transmit Timing