ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 7-39 and Table 7-40 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 7-29, Figure 7-30 and Figure 7-31).
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| 10 | tPDH | Presence pulse delay high | 15 | 60 | µs |
| 11 | tPDL | Presence pulse delay low | 60 | 240 | µs |
| 12 | tRDV | Read data valid time | tLOWR | 15 | µs |
| 13 | tREL | Read data release time | 0 | 45 | µs |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| 14 | tRSTL | Reset time low | 480 | 960 | µs |
| 15 | tRSTH | Reset time high | 480 | µs | |
| 16 | tSLOT | Bit cycle time | 60 | 120 | µs |
| 17 | tLOW1 | Write bit-one time | 1 | 15 | µs |
| 18 | tLOW0 | Write bit-zero time(2) | 60 | 120 | µs |
| 19 | tREC | Recovery time | 1 | µs | |
| 20 | tLOWR | Read bit strobe time(1) | 1 | 15 | µs |
Figure 7-29 1-Wire—Break (Reset)
Figure 7-30 1-Wire—Read Bit (Data)
Figure 7-31 1-Wire—Write Bit-One Timing (Command / Address or Data)