10 Revision History
Changes from Revision B (January 2023) to Revision C (November 2024)
- Updated Pin 9 and Pin 21 pin descriptions and package
labelGo
- Table 5-1 Pin Functions: Updated MDIO pin description to include
link to Compliance Test Modes sectionGo
- Table 6-1 Pin Functions: Updated description for RX_D3 for SGMII
modeGo
- Table 6-1 Pin Functions: Updated Pin 15 description to include
register writes for programming Pin 15 as RX_DV and CRS_DVGo
- Table 6-1 Pin Functions: Clarified that RX_D3 and RX_D2 are not used
in RMII Slave modeGo
- Removed RGMII Timing Diagrams for Internal Delay Enabled and
Internal Delay Disabled modes and created a new RGMII Transmit Timing Diagram
for clarityGo
- Corrected description for register 0x310 Bit 6Go
- Corrected order of register writes for enabling data
generator/checkerGo
- Corrected RGMII Transmit Encoding table for Normal Data Transmission
and Transmit Error Propogation Go
- Updated Serial Management Interface section with better wording and
clarityGo
- Table 7-25. PHY Address Bootstraps: Corrected binary representations of PHY
addresses 0xC and 0xDGo
- Register 0x18, Bit 15 has been removedGo
- Register 0x60B has been removedGo
- Register 0x609 has been removedGo
- Register 0x603 has been removedGo
- Register 0x456, clarified Bit DescriptionGo
- Register 0x12, Bit 7 has been removedGo
- Register 0x1F, clarified Bit 15 and Bit 14 DescriptionGo
- Added general typical application diagramGo
- Updated RGMII Typical Application diagram to include 25MHz
inputGo
- Simplified and updated the Detailed Design Procedure and added a link to the
Schematic ChecklistGo
Changes from Revision A (December 2021) to Revision B (January 2023)
- 向特性列表中添加了“提供功能安全型”Go
- Table 6-1 Pin Functions: Changed TX_CLK description to include (50
ohm Driver) for MII transmit clock.Go
- Table 6-4 Pin States -TC10 SLEEP: Changed the PULL TYPE of Pin 16
CLKOUT from PD->noneGo
- Added line to CLKOUT/GPIO2's description about which registers to
program to disable switchingGo
- Added line to INT pin description. Reg 12-13 is recommended to be
read only when INT_N is LOWGo
- MDC clock rate changed from 25MHz->20MHz in Serial Management
Interface Section of Pin Function TableGo
- Updated Iozh to clarify mapping of Rx_Ctrl and Rx_ER pinsGo
- Removed Supply ramp delay offset: For all suppliesGo
- Power-Up Timing figure correctedGo
- PHY Operation State Diagram figure updatedGo
- Added Auto-clear note to register 0x18B[6]Go
- Added XI clock PPM TableGo
- Added Auto-clear note to register 0x18B[6]Go
- Register 0x63E, clarified Bit DescriptionGo
- Register 0x63D, clarified Bit DescriptionGo
- Register 0x63C, clarified Bit DescriptionGo
- Register 0x63B, clarified Bit DescriptionGo
- Register 0x63A, clarified Bit DescriptionGo
- Register 0x639, clarified Bit DescriptionGo
- Register 0x451, clarified Bit Descriptions Go
- Register 0x18B has been addedGo
- Register 0x12, Bit 15 has been removedGo
Changes from Revision * (April 2021) to Revision A (December 2021)