ZHCSLL6C April 2021 – November 2024 DP83TC812R-Q1 , DP83TC812S-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
6.7 Timing Diagrams
Figure 6-1 MII Timing
Figure 6-2 RMII Transmit and Receive Timing
Figure 6-3 RGMII
Transmit Timing
Figure 6-4 RGMII Receive Timing (Internal Delay Enabled)
Figure 6-5 RGMII Receive Timing (Internal Delay Disabled)
Figure 6-6 Serial Management Timing
Figure 6-7 Power-Up
Timing
Figure 6-8 Reset Timing
Figure 6-9 WAKE Timing