ZHCSLL6C April 2021 – November 2024 DP83TC812R-Q1 , DP83TC812S-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHA|36
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHA|36
訂購信息
7.4.12.3 Reduced Gigabit Media Independent Interface
The DP83TC812-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by RGMII version 2.0 with LVCMOS. RGMII is designed to reduce the number of pins required to connect MAC and PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to sample the control signal pin on transmit and receive paths. Data is samples on just the rising edge of the clock. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25MHz.
The RGMII signals are summarized in Table 7-11:
| FUNCTION | PINS |
|---|---|
| Data Signals | TX_D[3:0] |
| RX_D[3:0] | |
| Control Signals | TX_CTRL |
| RX_CTRL | |
| Clock Signals | TX_CLK |
| RX_CLK |
Figure 7-16 RGMII Connections| TX_CTRL (POSITIVE EDGE) | TX_CTRL (NEGATIVE EDGE) | TX_D[3:0] | DESCRIPTION |
|---|---|---|---|
| 0 | 0 | 0000 through 1111 | Normal Inter-Frame |
| 0 | 1 | 0000 through 1111 | Reserved |
| 1 | 1 | 0000 through 1111 | Normal Data Transmission |
| 1 | 0 | 0000 through 1111 | Transmit Error Propagation |
| RX_CTRL (POSITIVE EDGE) | RX_CTRL (NEGATIVE EDGE) | RX_D[3:0] | DESCRIPTION |
|---|---|---|---|
| 0 | 0 | 0000 through 1111 | Normal Inter-Frame |
| 0 | 1 | 0000 through 1101 | Reserved |
| 0 | 1 | 1110 | False Carrier Indication |
| 0 | 1 | 1111 | Reserved |
| 1 | 0 | 0000 through 1111 | Normal Data Reception |
| 1 | 1 | 0000 through 1111 | Data Reception with Errors |
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the transition from the internal free running clock to a recovered clock (data synchronous). Data may be duplicated on the falling edge of the clock because double data rate (DDR) is only required for 1-Gbps operation, which is not supported by the DP83TC812-Q1.
The DP83TC812-Q1 supports in-band status indication to help simplify link status detection. Inter-frame signals on RX_D[3:0] pins as specified in Table 7-14.
| RX_CTRL | RX_D3 | RX_D[2:1] | RX_D0 |
|---|---|---|---|
| 00
Note: In-band status is only valid when RX_CTRL is low | Duplex Status: 0 = Half-Duplex 1 = Full-Duplex | RX_CLK Clock Speed: 00 = 2.5MHz 01 = 25MHz 10 = 125MHz 11 = Reserved | Link Status: 0 = Link not established 1 = Valid link established |