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ZHCS927G May 2012 – January 2018 CDCM6208

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RGZ|48
- MPQF123F

散熱焊盤機械數據 (封裝 | 引腳)

RGZ|48
- QFND014T

訂購信息

5 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

(Top View)

CDCM6208 CDCM6208_Pin_Assignments_SCAS931.gif

Pin Functions

PIN		I/O	TYPE	DESCRIPTION
NAME	NO.	I/O	TYPE	DESCRIPTION
PRI_REFP	8	Input	Universal	Primary Reference Input +
PRI_REFN	9	Input	Universal	Primary Reference Input –
VDD_PRI_REF	7	PWR	Analog	Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V, or connected to VDD_SEC_REF.
SEC_REFP	11	Input	Universal	Secondary Reference Input +
SEC_REFN	12	Input	Universal	Secondary Reference Input –
VDD_SEC_REF	10	PWR	Analog	Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V, or connected to VDD_PRI_REF⁽²⁾.
REF_SEL	6	Input	LVCMOS with 50-kΩ pullup	Manual Reference Selection MUX for PLL. In SPI or I²C mode the reference selection is also controlled through Register 4 bit 12.REF_SEL = 0 (≤ V_IL): selects PRI_REFREF_SEL = 1 (≥ V_IH): selects SEC_REF (when Reg 4.12 = 1). See Table 5 for detail.
ELF	41	Output	Analog	External loop filter pin for PLL
Y0_P	14	Output	Universal	Output 0 Positive Pin
Y0_N	15	Output	Universal	Output 0 Negative Pin
Y1_P	17	Output	Universal	Output 1 Positive Pin
Y1_N	16	Output	Universal	Output 1 Negative Pin
VDD_Y0_Y1 (2 pins)	13, 18	PWR	Analog	Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V, or 3.3 V
Y2_P	20	Output	Universal	Output 2 Positive Pin
Y2_N	21	Output	Universal	Output 2 Negative Pin
Y3_P	23	Output	Universal	Output 3 Positive Pin
Y3_N	22	Output	Universal	Output 3 Negative Pin
VDD_Y2_Y3 (2 pins)	19, 24	PWR	Analog	Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V, or 3.3 V
Y4_P	26	Output	Universal	Output 4 Positive Pin
Y4_N	25	Output	Universal	Output 4 Negative Pin
VDD_Y4	27	PWR	Analog	Supply pin for output 4 to set between 1.8 V, 2.5 V, or 3.3 V
Y5_P	29	Output	Universal	Output 5 Positive Pin
Y5_N	28	Output	Universal	Output 5 Negative Pin
VDD_Y5	30	PWR	Analog	Supply pin for output 5 to set between 1.8 V, 2.5 V, or 3.3 V
Y6_P	32	Output	Universal	Output 6 Positive Pin
Y6_N	33	Output	Universal	Output 6 Negative Pin
VDD_Y6	31	PWR	Analog	Supply pin for output 6 to set between 1.8 V, 2.5 V, or 3.3 V
Y7_P	35	Output	Universal	Output 7 Positive Pin
Y7_N	36	Output	Universal	Output 7 Negative Pin
VDD_Y7	34	PWR	Analog	Supply pin for output 7 to set between 1.8 V, 2.5 V, or 3.3 V
VDD_VCO	39	PWR	Analog	Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The supply of this pin and the VDD_PLL2 supply pin can be combined as they are both analog and sensitive supplies;
VDD_PLL1	37	PWR	Analog	Analog Power Supply Connections
VDD_PLL2	38	PWR	Analog	Analog Power Supply Connections; This pin is sensitive to power supply noise; The supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both power-sensitive, analog supply pins
DVDD	48	PWR	Analog	Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs.
GND	PAD	PWR	Analog	Power Supply Ground and Thermal Pad
STATUS0	46	Output	LVCMOS	Status pin 0 (see Table 12 for details)
STATUS1/PIN0	45	Output and Input	LVCMOS no pull resistor	STATUS1: Status pin in SPI/I²C modes. For details, see Table 10 for pin modes and Table 12 for status mode. PIN0: Control pin 0 in pin mode.
SI_MODE1	47	Input	LVCMOS with 50-kΩ pullup	Serial Interface Mode or Pin mode selection. SI_MODE[1:0]=00: SPI mode; SI_MODE[1:0]=01: I²C mode; SI_MODE[1:0]=10: Pin Mode (No serial programming); SI_MODE[1:0]=11: RESERVED
SI_MODE0	1		LVCMOS with 50-kΩ pulldown
SDI/SDA/PIN1	2	I/O	LVCMOS in Open drain out LVCMOS in no pull resistor	SDI: SPI Serial Data Input SDA: I²C Serial Data (Read/Write bidirectional), open-drain output; requires a pullup resistor in I²C mode; PIN1: Control pin 1 in pin mode
SDO/AD0/PIN2	3	Output/Input	LVCMOS out LVCMOS in LVCMOS in no pull resistor	SDO: SPI Serial Data AD0: I²C Address Offset Bit 0 input; PIN2: Control pin 2 in pin mode
SCS/AD1/PIN 3	4	Input	LVCMOS no pull resistor	SCS: SPI Latch EnableAD1: I²C Address Offset Bit 1 input; PIN3: Control pin 3 in pin mode
SCL/PIN4	5	Input	LVCMOS no pull resistor	SCL: SPI/I²C ClockPIN4: Control pin 4 in pin mode
RESETN/PWR	44	Input	LVCMOS with 50-kΩ pullup	In SPI/I²C programming mode, external RESETN signal (active low). RESETN = V _IL: device in reset (registers values are retained) RESETN = V _IH: device active. The device can be programmed through SPI while RESETN is held low (this is useful to avoid any false output frequencies at power up). ⁽¹⁾ In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3 V.
REG_CAP	40	Output	Analog	Regulator Capacitor; connect a 10-µF cap with ESR below 1 Ω to GND at frequencies above 100 kHz
PDN	43	Input	LVCMOS with 50-kΩ pullup	Power Down Active low. When PDN = V_IH is normal operation. When PDN = V_IL, the device is disabled and current consumption minimized. Exiting power down resets the entire device and defaults all registers. It is recommended to connect a capacitor to GND to hold the device in power-down until the digital and PLL related power supplies are stable. See section on power down in the application section.
SYNCN	42	Input	LVCMOS with 50-kΩ pullup	Active low. Device outputs are synchronized on a low-to-high transition on the SYNCN pin. SYNCN held low disables all outputs.

(1) Note: the device cannot be programmed in I²C while RESETN is held low.

(2) If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.