8.3 Feature Description

Supply Voltage: The CDCM6208 supply is internally regulated. Therefore, each core and I/O supply can be mixed and matched in any order according to the application needs. The device jitter performance is independent of supply voltage.

Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and VCO that operates from 2.39 GHz to 2.55 GHz (CDCM6208V1) and 2.94 GHz to 3.13 GHz (CDCM6208V2).

Reference inputs: The primary and secondary reference inputs support differential and single ended signals from 8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is a 4-bit reference divider available on the primary reference input. The input mux between the two references supports simply switching or can be configured as Smart MUX and supports glitchless input switching.

Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an output MUX. A total of 2 output MUXes are available.

Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz. The charge pump gain is programmable and the loop filter consists of internal + partially external passive components and supports bandwidths from a few Hz up to 400 kHz.

Phase Noise: The Phase Noise performance of the device can be summarized to:

Spurious Performance: The spurious performance is as follows:

• Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
• Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential signaling level operated at 122.88 MHz output frequency in the Nyquist range.

Device outputs:

The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML), low-swing CML (LVDS like), HCSL, and LVCMOS signaling.

Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.

Device Configuration: 32 distinct pin modes are available that cover many common use cases without the need for any serial programming of the device. For maximum flexibility the device also supports SPI and I²C programming. I²C offers 4 distinct addresses to support up to 4 devices on the same programming lines.

Figure 26. Typical Use Case: CDCM6208 Example in Wireless Infrastructure Baseband Application