SCAS859F January 2009 – June 2015 CDCLVP111
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- RHB|32
訂購信息
8 Detailed Description
8.1 Overview
The CDCLVP111 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 8 (a and b) for VCC = 2.5 V and Figure 9 (a and b) for VCC = 3.3 V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
8.2 Functional Block Diagram
8.3 Feature Description
The CDCLVP111 is a low-additive jitter universal to LVPECL fan out buffer with 2 selectable inputs. The small package, low-output skew, and low-additive jitter make for a flexible device in demanding applications.
8.4 Device Functional Modes
Select Input Terminal By CLK_SEL Pin
Table 1. Function Table
| CLK_SEL | ACTIVE CLOCK INPUT |
|---|---|
| 0 | CLK0, CLK0 |
| 1 | CLK1, CLK1 |
The two inputs of the CDCLVP111 are internally mixed together and can be selected through the control pin. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the CDCLVP111 to provide greater system flexibility.