ZHCSMV0A August 2021 – May 2022 CDCDB803
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| SMBUS-COMPATIBLE INTERFACE TIMING | ||||||
| fSMB | SMBus operating frequency | 10 | 400 | kHz | ||
| tBUF | Bus free time between STOP and START | 4.7 | μs | |||
| tHD_STA | START condition hold time | SMBCLK low after SMBDAT low | 4 | |||
| tSU_STA | START condition setup time | SMBCLK high before SMBDAT low | 4.7 | |||
| tSU_STO | STOP condition setup time | 4 | ||||
| tHD_DAT | SMBDAT hold time | 300 | ns | |||
| tSU_DAT | SMBDAT setup time | 250 | ||||
| tTIMEOUT | Detect SMBCLK low timeout | In terms of device input clock frequency | 1e6 | cycles | ||
| tLOW | SMBCLK low period | 4.7 | μs | |||
| tHIGH | SMBCLK high period | 4 | 50 | |||
| tF | SMBCLK/SMBDAT fall time(1) | 300 | ns | |||
| tR | SMBCLK/SMBDAT rise time(2) | 1000 | ||||