ZHCSMV0A August 2021 – May 2022 CDCDB803
PRODUCTION DATA
| PIN | TYPE(2) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| INPUT CLOCK | |||
| CLKIN_P | 3 | I | LP-HCSL differential clock input. Typically connected directly to the differential output of clock source. |
| CLKIN_N | 4 | I | |
| OUTPUT CLOCKS | |||
| CK0_P | 13 | O | LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK0_N | 14 | O | |
| CK1_P | 16 | O | LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK1_N | 17 | O | |
| CK2_P | 21 | O | LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK2_N | 22 | O | |
| CK3_P | 25 | O | LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK3_N | 26 | O | |
| CK4_P | 28 | O | LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK4_N | 29 | O | |
| CK5_P | 32 | O | LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK5_N | 33 | O | |
| CK6_P | 35 | O | LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK6_N | 36 | O | |
| CK7_P | 39 | O | LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect. |
| CK7_N | 40 | O | |
| MANAGEMENT AND CONTROL(1) | |||
| CKPWRGD_PD# | 1 | I, S, PD | Clock Power Good and Power Down multi-function input pin with internal 180-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. After PWRGD has been asserted high for the first time, the pin becomes a PD# pin and it controls power-down mode: LOW: Power-down mode, all output channels tri-stated. HIGH: Normal operation mode. |
| OE0# | 12 | I, S, PD | Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 0. HIGH: disable output channel 0. |
| OE1# | 18 | I, S, PD | Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 1. HIGH: disable output channel 1. |
| OE2# | 23 | I, S, PD | Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 2. HIGH: disable output channel 2. |
| OE3# | 24 | I, S, PD | Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 3. HIGH: disable output channel 3. |
| OE4# | 30 | I, S, PD | Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 4. HIGH: disable output channel 4. |
| OE5# | 31 | I, S, PD | Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 5. HIGH: disable output channel 5. |
| OE6# | 37 | I, S, PD | Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 6. HIGH: disable output channel 6. |
| OE7# | 41 | I, S, PD | Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 7. HIGH: disable output channel 7. |
| SMBUS AND SMBUS ADDRESS | |||
SADR0 | 5 | I, S, PU / PD | SMBus address strap
bit[0]. This is a 3-level input that is decoded in conjunction with
pin 8 to set SMBus address. It has internal 180-kΩ pullup / pulldown
network biasing to GND when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration input, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground. |
| SMBDAT | 6 | I / O | Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. |
| SMBCLK | 7 | I | Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. |
| SADR1 | 8 | I, S, PU / PD | SMBus address strap
bit[1]. This is a 3-level input that is decoded in conjunction with
pin B4 to set SMBus address. It has internal 180-kΩ pullup /
pulldown network biasing to GND when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground. |
| SMBWRTLOCK | 46 | I, PD | SMBWRTLOCK: Disables
write commands on SMBus. All writes will be ignored when SMBWRTLOCK
is asserted (reads are not affected). Internal 180-kΩ pulldown,
active high. 0 = SMBus write enabled. 1 = SMBus write disabled. |
| SUPPLY VOLTAGE AND GROUND | |||
| VDDR | 2 | P | Power supply input for input clock receiver. Connect to 3.3-V power supply rail with decoupling capacitor to GND. Place a 0.1-μF capacitor close to each supply pin between power supply and ground. |
| VDD | 11, 15, 19, 27, 34, 38, 42, 44 | P | 3.3-V power supply for output channels and core voltage. |
| GND | DAP | G | Ground. Connect ground pad to system ground. |
| NO CONNECT | |||
| NC | 9, 10, 20, 43, 45 | — | Do not connect to GND or VDD. |
| NC | 47, 48 | — | No connect. Pins may be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings. |