ZHCSMV0A August 2021 – May 2022 CDCDB803
PRODUCTION DATA
Table 8-4 lists the CDCDB803 registers. All register locations not listed in Table 8-4 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | RCR1 | Reserved Control Register 1 | Go |
| 1h | OECR1 | Output Enable Control 1 | Go |
| 2h | OECR2 | Output Enable Control 2 | Go |
| 3h | OERDBK | Output Enable# Pin Read Back | Go |
| 4h | RCR2 | Reserved Control Register 2 | Go |
| 5h | VDRREVID | Vendor/Revision Identification | Go |
| 6h | DEVID | Device Identification | Go |
| 7h | BTRDCNT | Byte Read Count Control | Go |
| 8h | OUTSET | Output Setting Control | Go |
| 4Ch | CAPTRIM | Slew Rate Capacitor Cluster 1 & 2 | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
RCR1 is shown in Table 8-6.
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The RCR1 register contains reserved bits.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | Reserved | R | 4h | Reserved. |
| 3-0 | Reserved | R/W | 7h | Writing to these bits will not affect the functionality of the device. |
OECR1 is shown in Table 8-7.
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The OECR1 register contains bits that enable or disable individual output clock channels [5:0].
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | OUT_EN_CLK5 | R/W | 1h | This bit controls the output enable
signal for output channel CK5_P/CK5_N. 0h = Output Disabled 1h = Output Enabled |
| 6 | OUT_EN_CLK4 | R/W | 1h | This bit controls the output enable
signal for output channel CK4_P/CK4_N. 0h = Output Disabled 1h = Output Enabled |
| 5 | OUT_EN_CLK3 | R/W | 1h | This bit controls the output enable
signal for output channel CK3_P/CK3_N. 0h = Output Disabled 1h = Output Enabled |
| 4 | OUT_EN_CLK2 | R/W | 1h | This bit controls the output enable
signal for output channel CK2_P/CK2_N. 0h = Output Disabled 1h = Output Enabled |
| 3 | Reserved | R/W | 1h | Writing to this bit will not affect the functionality of the device. |
| 2 | OUT_EN_CLK1 | R/W | 1h | This bit controls the output enable
signal for output channel CK1_P/CK1_N. 0h = Output Disabled 1h = Output Enabled |
| 1 | OUT_EN_CLK0 | R/W | 1h | This bit controls the output enable
signal for output channel CK0_P/CK0_N. 0h = Output Disabled 1h = Output Enabled |
| 0 | Reserved | R/W | 1h | Writing to this bit will not affect the functionality of the device. |
OECR2 is shown in Table 8-8.
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The OECR2 register contains bits that enable or disable individual output clock channels [7:6].
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | Reserved | R/W | 1h | Writing to these bits will not affect the functionality of the device. |
| 2 | OUT_EN_CLK7 | R/W | 1h | This bit controls the output enable
signal for output channel CK7_P/CK7_N. 0h = Output Disabled 1h = Output Enabled |
| 1 | Reserved | R/W | 1h | Writing to this bit will not affect the functionality of the device. |
| 0 | OUT_EN_CLK6 | R/W | 1h | This bit controls the output enable
signal for output channel CK6_P/CK6_N. 0h = Output Disabled 1h = Output Enabled |
OERDBK is shown in Table 8-9.
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The OERDBK register contains bits that report the current state of the OE[7:0]# input pins.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RB_OE7 | R | 0h | This bit reports the logic level present on the OE7# pin. |
| 6 | RB_OE6 | R | 0h | This bit reports the logic level present on the OE6# pin. |
| 5 | RB_OE5 | R | 0h | This bit reports the logic level present on the OE5# pin. |
| 4 | RB_OE4 | R | 0h | This bit reports the logic level present on the OE4# pin. |
| 3 | RB_OE3 | R | 0h | This bit reports the logic level present on the OE3# pin. |
| 2 | RB_OE2 | R | 0h | This bit reports the logic level present on the OE2# pin. |
| 1 | RB_OE1 | R | 0h | This bit reports the logic level present on the OE1# pin. |
| 0 | RB_OE0 | R | 0h | This bit reports the logic level present on the OE0# pin. |
RCR2 is shown in Table 8-10.
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The RCR2 register contains reserved bits.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | Reserved | R | 0h | Reserved. |
VDRREVID is shown in Table 8-11.
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The VDRREVID register contains a vendor identification code and silicon revision code.| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | REV_ID | R | 0h | Silicon revision code. Silicon revision code bits [3:0] map to register bits [7:4] directly. |
| 3-0 | VENDOR_ID | R | Ah | Vendor identification code. Vendor ID bits [3:0] map to register bits [3:0] directly. |
DEVID is shown in Table 8-12.
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The DEVID register contains a device identification code.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | DEV_ID | R | E7h | Device ID code. Device ID bits[7:0] map to register bits[7:0] directly. |
BTRDCNT is shown in Table 8-13.
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The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | Reserved | R/W | 0h | Writing to these bits will not affect the functionality of the device. |
| 4 | BYTE_COUNTER | R/W | 0h | Writing to this register configures how many bytes will be read back. |
| 3-0 | BYTE_COUNTER | R/W | 8h |
OUTSET is shown in Table 8-14.
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Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down state for all outputs. The remaining bits for this register are reserved.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | Reserved | R | 0h | Reserved. |
| 5 | CH_ZOUT_SEL | R/W | 0h | Select between 85 ? (0) and 100 ? (1) Output impedance |
| 4 | d_DRIVE_OP_STATE_CTRL | R/W | 0h | Power-down state of all output
clocks. 0: LOW/LOW 1: TRI_STATE |
| 3-0 | Reserved | R/W | 0h | Register bits can be written to 0. Writing a different value than 0 will affect device functionality. |
CAPTRIM is shown in Table 8-16.
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Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control the slew rate for output channel cluster 1. Refer below for cluster identification.
| Cluster | Outputs |
|---|---|
| 1 | CK3, CK2, CK1, CK0 |
| 2 | CK7, CK6, CK5, CK4 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | CLUSTER2_CAP_TRIM | R/W | 6h | Slew Rate Reduction Cap Trim for
Cluster 2. Default value of 6h. 0: minimum F: maximum |
| 3-0 | CLUSTER1_CAP_TRIM | R/W | 6h | Slew Rate Reduction Cap Trim for
Cluster 1. Default value of 6h. 0: minimum F: maximum |