The device allows direct disabling of the CHG and DSG drivers through the CTRC and CTRD pins, respectively. Figure 9-10 shows the operation of the CTRC and CTRD pins. To support the simple-stack solution for higher-cell count packs, these pins are designed to operate above the device’s VDD level. Connect a 10-MΩ resistor between a lower device CTRC and CTRD input pins to an upper device's CHG and DSG output pins (see the schematics in Section 9.3.13).

CTRC only enables or disables the CHG pin, while CTRD only enables or disables the DSG pin. When the CTRx pin is in the DISABLED region, the respective FET pin is off, regardless of the state of the protection circuitry. When the CTRx pin is in either ENABLED region, the protection circuitry determines the state of the FET driver.

Both CTRx pins apply the fault-detection filtered method to improve the robustness of the signal detection. The counter counts up if an ENABLED signal is sampled; the counter counts down if a DISABLED signal is sampled. When the counter counts up from 0% to > 70% of its full range, which takes about 7-ms typical of a solid signal, the CTRx pins take the signal as ENABLED. If the counter counts down from 100% to < 30% of its full range, which takes about 7-ms typical of a solid signal, the CTRx pins take the signal as DISABLED. From a 0 count counter (solid DISABLE), a solid ENABLE signal takes about t_{CTRDEG_ON} time to deglitch. From a 100% count (solid ENABLE), a solid DISABLE signal takes about t_{CTRDEG_OFF} time to deglitch. Although such a filter scheme provides a certain level of noise tolerance, it is highly recommended to shield the CTRx traces and keep the traces as short as possible in the PCB layout design. The CTRx deglitch time will add onto the FET response timing on OV, UV, and OW faults in a stack configuration. The t_{CTRDEG_OFF} time adds an additional delay to the fault detection timing and the t_{CTRDEG_ON} time adds an additional delay to the fault recovery timing.

Figure 9-10 CTRC, CTRD Voltage Levels