ZHCSHU6L march 2018 – august 2023 BQ77915
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Protection Summary
- 9.3.2
Fault Operation
- 9.3.2.1 Operation in OV
- 9.3.2.2 Operation in UV
- 9.3.2.3 Operation in OW
- 9.3.2.4 Operation in OCD1
- 9.3.2.5 Operation in OCD2
- 9.3.2.6 Programming the OCD1/2 Delay Using the OCDP Pin
- 9.3.2.7 Operation in SCD
- 9.3.2.8 Operation in OCC
- 9.3.2.9 Overcurrent Recovery Timer
- 9.3.2.10 Load Detection and Load Removal Detection
- 9.3.2.11 Operation in OTC
- 9.3.2.12 Operation in OTD
- 9.3.2.13 Operation in UTC
- 9.3.2.14 Operation in UTD
- 9.3.3 Protection Response and Recovery Summary
- 9.3.4 Cell Balancing
- 9.3.5 HIBERNATE Mode Operation
- 9.3.6 Configuration CRC Check and Comparator Built-In-Self-Test
- 9.3.7 Fault Detection Method
- 9.3.8 State Comparator
- 9.3.9 DSG FET Driver Operation
- 9.3.10 CHG FET Driver Operation
- 9.3.11 External Override of CHG and DSG Drivers
- 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
- 9.3.13 Stacking Implementations
- 9.3.14 Zero-Volt Battery Charging Inhibition
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1
Application Information
- 10.1.1 Recommended System Implementation
- 10.2 Typical Application
- 10.1
Application Information
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
10.1.1.1 CHG and DSG FET Rise and Fall Time
The CHG and DSG FET drivers are designed to have fast switching time. Customers should select a proper gate resistor (RCHG and RDSG in the reference schematic) to set to the desired rise/fall time.
Figure 10-1 Select Proper Gate Resistor for FET Rise and Fall TimeThe CHG FET fall time is generally slower because it is connected to the PACK– terminal. The CHG driver will pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or Vgsth, the PACK– will start to fall below ground, the CHG signal will follow suit in order to turn off the CHG FET. This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel, and the value of the gate-source resistor (RGS_CHG).
Figure 10-2 CHG FET Fall Time