5 Pin Configuration and Functions

BQ25618 BQ25619 BQ25618 YFF Package30-Pin WCSPTop View

Figure 5-1 BQ25618 YFF Package30-Pin WCSPTop View

BQ25618 BQ25619 BQ25619 RTW Package24-Pin WQFNTop View

Figure 5-2 BQ25619 RTW Package24-Pin WQFNTop View

Table 5-1 Pin Functions

PIN			TYPE⁽¹⁾	DESCRIPTION
NAME	BQ25618 NO.	BQ25619 NO.	TYPE⁽¹⁾	DESCRIPTION
BAT	C1, D1, E1, F1	13	P	Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 μF closely to the BAT pin.
BAT	C1, D1, E1, F1	14	P
BATSNS	F3	10	AIO	Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery voltage through BAT pin.
BTST	C3	21	P	PWM high-side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
CE	E3	9	DI	Charge enable pin. When this pin is driven LOW, battery charging is enabled.
GND	A1, B1	17	P	Ground
GND	A1, B1	18	P	Ground
INT	F4	7	DO	Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to the host to report charger device status and fault.
NC	B5	8		Not connected
PMID	A3, B3	23	DO	Boost mode output. Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Consider the total input capacitance, put 1 μF on VBUS to GND, and the rest capacitance on PMID to GND (typical 2x4.7 μF plus 1 nF).
PMID_GOOD	D5	3	DO	Open drain active high PMID good indicator. Connect to the pullup rail REGN through 10-kΩ resistor. HIGH indicates PMID voltage is below 5.2 V and the current through Q1 is below 110% of input current limit. This signal can be used to drive external PMOS FET to disconnect the PMID under charging load when Boost mode output voltage is too high or output current is too high.
PSEL	C5	2	DI	Power source selection input. HIGH indicates 500-mA input current limit. LOW indicates 2.4-A input current limit. Once the device gets into Host mode, the host can program a different input current limit to the IINDPM register.
QON	D4	12	DI	BATFET enable/reset control input. When the BATFET is in Ship mode, a logic LOW of t_SHIPMODE duration turns on BATFET to exit Ship mode. When the BATFET is not in Ship mode, a logic LOW of t_{QON_RST} (minimum 8 s) duration resets SYS (system power) by turning BATFET off for t_{BATFET_RST} (minimum 250 ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplug or not through I²C bit BATFET_RST_WVBUS. The pin is pulled up to V_BAT through 200 kΩ to maintain default HIGH logic during Ship mode. It has an internal clamp to 6.5 V.
REGN	C4	22	P	PWM low-side driver positive supply output. Internally, REGN is connected to the anode of the bootstrap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.
SCL	F5	5	DI	I²C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA	E4	6	DIO	I²C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT	E5	4	DO	Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-k? resistor. The STAT pin indicates charger status. Charge in progress: LOW Charge complete or charger in Sleep mode: HIGH Charge suspend (fault response): Blink at 1 Hz
SW	A2, B2	19	P	Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
SW	A2, B2	20	P
SYS	C2, D2, E2, F2	15	P	Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 μF (min) closely to the SYS pin.
SYS	C2, D2, E2, F2	16	P
TS	D3	11	AI	Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and Boost mode suspend when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor.
VAC	A5	1	AI	Input voltage sensing. This pin must be tied to VBUS.
VBUS	A4, B4	24	P	Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to IC.
Thermal Pad	—	—	P	Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P = Power