ZHCSKO3B January 2020 – September 2020 BQ25611D
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BAT | 13 | P | Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 μF(2) closely to the BAT pin. |
| 14 | |||
| BATSNS | 10 | AI | Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery voltage through BAT pin. |
| BTST | 21 | P | PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST. |
| CE | 9 | DI | Charge enable pin. When this pin is driven LOW, battery charging is enabled. |
| D+ | 2 | AIO | Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors. |
| D- | 3 | AIO | Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors. |
| GND | 17 | — | Ground. |
| 18 | |||
| INT | 7 | DO | Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to the host to report charger device status and fault. |
| NC | 8 | — | Not connected. |
| PMID | 23 | P | Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Place a 10-μF capacitor(2) on PMID to GND. |
| QON | 12 | DI | BATFET enable/reset control input. When the BATFET is in ship mode, a logic LOW of tSHIPMODE duration turns on BATFET to exit ship mode. When the BATFET is not in ship mode, a logic LOW of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplugged or not through I2C bit BATFET_RST_WVBUS. The pin is pulled up to VQON through 200 kΩ to maintain default HIGH logic during ship mode. It has an internal clamp to 6.5 V. QON pin is pulled through 200-kΩ resistor to VQON. VQON is supplied from VBUS minus 2 diode voltage drop or from VBAT minus 1 diode voltage drop. It has an internal voltage clamp to 6.5 V. |
| REGN | 22 | P | PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor(2) from REGN to analog GND. The capacitor should be placed close to the IC. |
| SCL | 5 | DI | I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
| SDA | 6 | DIO | I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor. |
| STAT | 4 | DO | Open-drain interrupt output. Connect the STAT pin to a logic rail
via 10-k? resistor. The STAT pin indicates charger status. Charge in progress: LOW. Charge complete or charger in SLEEP mode: HIGH. Charge suspend (fault response): blink at 1 Hz. |
| SW | 19 | P | Switching node connecting to output inductor. Internally, SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST. |
| 20 | |||
| SYS | 15 | P | System output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 μF (min)(2) closely to the SYS pin. |
| 16 | |||
| TS | 11 | AI | Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and boost mode suspended when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor. |
| VAC | 1 | P | Input voltage sensing. This pin must be tied to VBUS. |
| VBUS | 24 | P | Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor(2) from VBUS to GND and place it as close as possible to the device. |
| Thermal Pad | — | P | Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. |