ZHCSKO3B January 2020 – September 2020 BQ25611D
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Power-On-Reset (POR)
- 9.3.2 Device Power Up from Battery without Input Source
- 9.3.3 Power Up from Input Source
- 9.3.4 Boost Mode Operation From Battery
- 9.3.5 Power Path Management
- 9.3.6 Battery Charging Management
- 9.3.7 Ship Mode and QON Pin
- 9.3.8 Status Outputs ( STAT, INT )
- 9.3.9 Protections
- 9.3.10 Serial Interface
- 9.4 Device Functional Modes
- 9.5 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
9.3.5.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by SYS_Min bits. Even with a fully depleted battery, the system is regulated above the minimum system voltage.
When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system and battery is the VDS of the BATFET.
When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the system is always regulated at typically 50 mV above the battery voltage. The status register VSYS_STAT bit goes to 1 when the system is in minimum system voltage regulation.
Figure 9-1 System Voltage vs Battery Voltage