ZHCSPT0 June 2022 BQ25172
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DSG|8
訂購信息
5 Pin Configuration and Functions
Figure 5-1 DSG
PackageWSON
8-PinTop
ViewTable 5-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| IN | 1 | P | Input power, connected to external DC supply. Bypass IN with a ≥1-μF capacitor to GND, placed close to the IC. |
| ISET | 2 | I | Programs the device charge current. External resistor from ISET to GND defines charge current value. Expected range is 30 k? (10 mA) to 375 ? (800 mA). ICHG = KISET / RISET. |
| TS | 3 | I | Temperature qualification voltage input. Connect a negative temperature coefficient (NTC) thermistor directly from TS to GND (AT103-2 recommended). Charge suspends when the TS pin voltage is out of range. VOUT_OVP is reduced in cool region. If TS function is not needed, connect an external 10-kΩ resistor from this pin to GND. Pulling VTS < VTS_ENZ disables the charger. |
| GND | 4 | – | Ground pin |
| STAT | 5 | O | Open drain charge status indication output. Connect to the pullup rail via a 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When a fault condition is detected, the STAT pin blinks at 1 Hz. |
| TMR | 6 | I | Connect to a pulldown resistor to program charge safety timer duration. Valid resistor range is 3.6 kΩ to 36 kΩ. Refer to Section 7.3.1.2. |
| VSET | 7 | I | Programs the number of series NiMH cells. Valid resistor range is 3.6 kΩ to 62 kΩ. Recommend using a ±1% tolerance resistor with <200 ppm/oC temperature coefficient. Refer to Section 7.3.1.3. |
| OUT | 8 | P | Battery connection. System load may be connected in parallel to the battery. Bypass OUT with a ≥1-μF capacitor to GND, placed close to the IC. |
| Thermal Pad | — | — | Exposed pad beneath the IC for heat dissipation. Solder thermal pad to the board with vias connecting to solid GND plane. |