ZHCSKL0D December 2009 – December 2019 BQ24610 , BQ24617
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Battery Voltage Regulation
- 9.3.2 Battery Current Regulation
- 9.3.3 Input Adapter Current Regulation
- 9.3.4 Precharge
- 9.3.5 Charge Termination, Recharge, and Safety Timer
- 9.3.6 Power Up
- 9.3.7 Enable and Disable Charging
- 9.3.8 System Power Selector
- 9.3.9 Automatic Internal Soft-Start Charger Current
- 9.3.10 Converter Operation
- 9.3.11 Synchronous and Nonsynchronous Operation
- 9.3.12 Cycle-by-Cycle Charge Undercurrent Protection
- 9.3.13 Input Overvoltage Protection (ACOV)
- 9.3.14 Input Undervoltage Lockout (UVLO)
- 9.3.15 Battery Overvoltage Protection
- 9.3.16 Cycle-by-Cycle Charge Overcurrent Protection
- 9.3.17 Thermal Shutdown Protection
- 9.3.18 Temperature Qualification
- 9.3.19 Timer Fault Recovery
- 9.3.20 PG Output
- 9.3.21 CE (Charge Enable)
- 9.3.22 Charge Status Outputs
- 9.3.23 Battery Detection
- 9.4 Device Functional Modes
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
- RGE|24
散熱焊盤機械數據 (封裝 | 引腳)
- RGE|24
訂購信息
9.3.10 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with feed-forward control scheme. A type-III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 12 kHz to 17 kHz for BQ2461x, where the resonant frequency, fo, is given by:
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty cycle of the converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region. Also see Application and Implementation for how to select the inductor, capacitor, and MOSFET.