ZHCSQM2 May 2022 AMC1333M10
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fCLK | Internal clock frequency | 9.5 | 10 | 10.5 | MHz | |
| Internal clock duty cycle | 45% | 50% | 55% | |||
| tH | DOUT hold time after rising edge of CLKOUT | CLOAD = 15 pF | 3.5 | ns | ||
| tD | DOUT hold time after rising edge of CLKOUT | CLOAD = 15 pF | 15 | ns | ||
| tr | DOUT and CLKOUT rise time | 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF | 2.5 | 6 | ns | |
| 10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF | 3.2 | 6 | ||||
| tf | DOUT and CLKOUT fall time | 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF | 2.2 | 6 | ns | |
| 10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF | 2.9 | 6 | ||||
| tASTART | Device start-up time | AVDD step from 0 to 3.0 V with DVDD ≥ 2.7 V to bitstream valid, 0.1% settling | 0.25 | ms | ||