Figure 7-3 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC1333M10. The output V₅ of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage V_IN = (V_INN – V_INP), providing an analog voltage V₁ at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in an output voltage V₃ that is summed with the input signal V_IN and the output of the first integrator V₂. Depending on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V₅, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input.

The modulator shifts the quantization noise to high frequencies, as depicted in Figure 7-1. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's C2000? and Sitara? microcontroller families offer a suitable programmable, hardwired filter structure, termed a sigma-delta filter module (SDFM), optimized for usage with the AMC1333M10. Alternatively, a field-programmable gate array (FPGA) or complex programmable logic device (CPLD) can be used to implement the filter.