ZHCSX71 October 2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125
PRODUCTION DATA
| 參數(shù) | 測試條件 | 最小值 | 標稱值 | 最大值 | 單位 | |
|---|---|---|---|---|---|---|
| ADC 時序規(guī)格 | ||||||
| tAD | 孔徑延遲 | 0.5 | ns | |||
| tA | 孔徑抖動 | 具有快速邊緣的方波時鐘 | 250 | fs | ||
| tACQ | 信號采集周期，以采樣時鐘下降沿為基準 | -TS/5 |
采樣時鐘周期 | |||
| tCONV | 信號轉(zhuǎn)換周期，以采樣時鐘下降沿為基準 | Fs = 25MSPS | 5.5 | ns | ||
| Fs = 65MSPS | 5.5 | ns | ||||
| Fs = 125MSPS | 5.5 | ns | ||||
| 喚醒時間 | 斷電后的數(shù)據(jù)有效時間。內(nèi)部基準。 | 30 | us | |||
| ADC 延遲 | 信號輸入到數(shù)據(jù)輸出 | DDR | 1 | ADC 時鐘周期 | ||
| SDR | 1 | |||||
| 接口時序 - DDR CMOS | ||||||
| tPD | 傳播延遲：采樣時鐘下降沿到 DCLK 上升沿 | TS/4 + 3 | ns | |||
| tDE | DCLK 邊沿到上一個數(shù)據(jù)轉(zhuǎn)換 | Fs = 25MSPS | -10 | -9 | ns | |
| Fs = 65MSPS | -3.8 | -3.4 | ||||
| Fs = 125MSPS | -2 | -1.8 | ||||
| tDL | DCLK 邊沿到下一個數(shù)據(jù)轉(zhuǎn)換 | Fs = 25MSPS | 9 | 10 | ||
| Fs = 65MSPS | 3.4 | 3.8 | ||||
| Fs = 125MSPS | 1.8 | 2 | ||||
| 接口時序 - SDR CMOS | ||||||
| tPD | 傳播延遲：采樣時鐘下降沿到 DCLK 上升沿 | TS/4 + 3 | ns | |||
| tDE | DCLK 邊沿到上一個數(shù)據(jù)轉(zhuǎn)換 | Fs = 25MSPS | -20 | -18 | ns | |
| Fs = 65MSPS | -7.6 | -6.9 | ||||
| Fs = 125MSPS | -4 | -3.6 | ||||
| tDV | DCLK 邊沿到下一個數(shù)據(jù)轉(zhuǎn)換 | Fs = 25MSPS | 18 | 20 | ||
| Fs = 65MSPS | 6.9 | 7.7 | ||||
| Fs = 125MSPS | 3.6 | 4 | ||||