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ZHCSXJ8B December 2024 – June 2025 ADC3648 , ADC3649

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RTD|64
- MPQF141C

散熱焊盤機械數據 (封裝 | 引腳)

RTD|64
- QFND625

訂購信息

8.5.5 寄存器映射

表 8-18 寄存器映射摘要

寄存器地址	寄存器數據
A[11:0]	D7	D6	D5	D4	D3	D2	D1	D0
0x25	0	0	0	CFG RDY	0	0	0	0
0x100	0	0	0	0	0	0	0	復位
0x101	0	0	0	GBL PDN	0	0	0	0
0x102	0	SYSREF DET CLR	0	0	0	0	0	0
0x104	0	0	0	0	0	0	CHB TERM	CHA TERM
0x10A	0	0	0	0	0	OVR CLR		OVR STICKY
0x10B	OVR LENGTH
0x110	LVDS TERM	0	LVDS HALF SWING	0	0	0	SWAP CH	0
0x111	LVDS DATA INV [7:0]
0x112	LVDS DATA INV [15:8]
0x113	LVDS PDN [14:8]							0
0x114	0	0	0	0	0	0	0	LVDS PDN [15]
0x115	0	0	0	0	FCLK DC	FCLK DIS	0	0
0x116	LVDS MUX EN	LVDS SWAP EDGE	0	0	0	LVDS SCR
0x117	DOUT1 MUX				DOUT0 MUX
0x118	DOUT3 MUX				DOUT2 MUX
0x119	DOUT5 MUX				DOUT4 MUX
0x11A	DOUT7 MUX				DOUT6 MUX
0x11B	DOUT9 MUX				DOUT8 MUX
0x11C	DOUT11 MUX				DOUT10 MUX
0x11D	DOUT13 MUX				DOUT12 MUX
0x11E	DOUT15 MUX				DOUT14 MUX
0x132	HIGH FIN	0	0	0	0	0	0	0
0x140	0	SYSREF DET	SYSREF OR	SYSREF X5	SYSREF X4	SYSREF X3	SYSREF X2	SYSREF X1
0x146	0	0	0	GPIO 配置
0x14A	0	0	0	PATTERN CLK	0	TEST PATTERN
0x14B	CUSTOM PATTERN [7:0]
0x14C	CUSTOM PATTERN [15:8]
0x14D	0	0	0	0	CUSTOM PATTERN [19:16]
0x15B	DIGITAL GAIN CHA
0x15C	DIGITAL GAIN CHB
0x160	0	0	0	0	0	0	SYSREF MODE
0x161	LVDS SYSREF MASK		DDC SYSREF MASK		NCO SYSREF MASK		TIMER SYSREF MASK
0x162	SYSREF TIME STAMP		0	6dB GAIN OVERRIDE		COMPLEX DDC EN	OUTPUT RES	OUTPUT FORMAT
0x163	DDC3 MUX		DDC2 MUX		DDC1 MUX		DDC0 MUX
0x164	NCO3 UPDATE	NCO2 UPDATE	NCO1 UPDATE	NCO0 UPDATE	SEL NEG IM	0	0	NCO MODE
0x165	0	0	0	LOW LATENCY EN	0	DIS NCO AUTO UPDATE	NCO SEL EN	NCO COMMON UPDATE
0x166	DDC3 NCO SEL		DDC2 NCO SEL		DDC1 NCO SEL		DDC0 NCO SEL
0x167	DDC1 DECIMATION				DDC0 DECIMATION
0x168	DDC3 DECIMATION				DDC2 DECIMATION
0x169	UNEQUAL DECIMATION	0	NUM OF DDCS		COMMON DECIMATION
0x16B	0	0	UPDATE NYQUIST ZONE	0	0	NYQUIST_ZONE
0x205..0x200	DDC0 NCO FREQUENCY0 [47:0]
0x20B..0x206	DDC0 NCO FREQUENCY1 [47:0]
0x211..0x20C	DDC0 NCO FREQUENCY2 [47:0]
0x217..0x212	DDC0 NCO FREQUENCY3 [47:0]
0x219/0x218	DDC0 NCO PHASE0 [15:0]
0x21B/0x21A	DDC0 NCO PHASE1 [15:0]
0x21D/0x21C	DDC0 NCO PHASE2 [15:0]
0x21F/0x21E	DDC0 NCO PHASE3 [15:0]
0x245..0x240	DDC1 NCO FREQUENCY0 [47:0]
0x24B..0x246	DDC1 NCO FREQUENCY1 [47:0]
0x251..0x24C	DDC1 NCO FREQUENCY2 [47:0]
0x257..0x252	DDC1 NCO FREQUENCY3 [47:0]
0x259/0x258	DDC1 NCO PHASE0 [15:0]
0x25B/0x25A	DDC1 NCO PHASE1 [15:0]
0x25D/0x25C	DDC1 NCO PHASE2 [15:0]
0x25F/0x25E	DDC1 NCO PHASE3 [15:0]
0x285..0x280	DDC2 NCO FREQUENCY0 [47:0]
0x28B..0x286	DDC2 NCO FREQUENCY1 [47:0]
0x291..0x28C	DDC2 NCO FREQUENCY2 [47:0]
0x297..0x292	DDC2 NCO FREQUENCY3 [47:0]
0x299/0x298	DDC2 NCO PHASE0 [15:0]
0x29B/0x29A	DDC2 NCO PHASE1 [15:0]
0x29D/0x29C	DDC2 NCO PHASE2 [15:0]
0x29F/0x29E	DDC2 NCO PHASE3 [15:0]
0x2C5...0x2C0	DDC3 NCO FREQUENCY0 [47:0]
0x2CB..0x2C6	DDC3 NCO FREQUENCY1 [47:0]
0x2D1..0x2CC	DDC3 NCO FREQUENCY2 [47:0]
0x2D7..0x2D2	DDC3 NCO FREQUENCY3 [47:0]
0x2D9/0x2D8	DDC3 NCO PHASE0 [15:0]
0x2DB/0x2DA	DDC3 NCO PHASE1 [15:0]
0x2DD/0x2DC	DDC3 NCO PHASE1 [15:0]
0x2DF/0x2DE	DDC3 NCO PHASE3 [15:0]
0x590	0	0	0	0	0	0	ENABLE DCLK DIVIDER	0
0x691	LVDS PDN [5:7]			DCLK PD	0	0	0	0
0x692	0	0	0	LVDS PDN [0:4]