ZHCSPO2 September 2023 ADC32RF52
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - AC Specifications (Dither ENABLED)
- 6.9 Timing Requirements
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 功能方框圖
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTD|64
訂購(gòu)信息
8.2.1.3 Application Curves
The following application curves demonstrate performance and results only of the ADC using a balun front end and configured to 4x internal averaging. The input frequency is 900 MHz (FS = 2.6 GSPS) and input amplitudes of -6 and -20 dBFS are shown with dither enabled/disabled.
| AIN = -6 dBFS, Dither DIS SNR = 67.8 dBFS, HD23 = 81 dBFS, Non HD23 = 76 dBFS |
| AIN = -20 dBFS, Dither = DIS SNR = 70.2 dBFS, SFDR = 58 dBc, Non HD23 = 85 dBFS |
| AIN = -6 dBFS, Dither EN SNR = 67.7 dBFS, HD23 = 80 dBFS, Non HD23 = 76 dBFS |
| AIN = -20 dBFS, Dither = EN SNR = 69.5 dBFS, HD23 = 67 dBc, Non HD23 = 88 dBFS |