ZHCSPO2 September 2023 ADC32RF52
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications (Dither DISABLED)
- 6.8 Electrical Characteristics - AC Specifications (Dither ENABLED)
- 6.9 Timing Requirements
- 6.10 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 功能方框圖
- 7.3
Feature Description
- 7.3.1 Analog Inputs
- 7.3.2 Sampling Clock Input
- 7.3.3 SYSREF
- 7.3.4 ADC Foreground Calibration
- 7.3.5 Decimation Filter
- 7.3.6
JESD204B Interface
- 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
- 7.3.6.2 JESD204B Frame Assembly
- 7.3.6.3 JESD204B Frame Assembly in Bypass Mode
- 7.3.6.4 JESD204B Frame Assembly with Complex Decimation - Single Band
- 7.3.6.5 JESD204B Frame Assembly with Complex Decimation - Dual Band
- 7.3.6.6 JESD204B Frame Assembly with Complex Decimation - Quad Band
- 7.3.7 SERDES Output MUX
- 7.3.8 Test Pattern
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6 Register Maps
-
8 Application and Implementation
- 8.1 Application Information
- 8.2 Typical Applications
- 8.3
Initialization Set Up
- 8.3.1
Initial Device Configuration After Power-Up
- 8.3.1.1 STEP 1: RESET
- 8.3.1.2 STEP 2: Device Configuration
- 8.3.1.3 STEP 3: JESD Interface Configuration (1)
- 8.3.1.4 STEP 4: SYSREF Synchronization
- 8.3.1.5 STEP 5: JESD Interface Configuration (2)
- 8.3.1.6 STEP 6: Analog Trim Settings
- 8.3.1.7 STEP 7: Calibration Configuration
- 8.3.1.8 STEP 8: SYSREF Synchronization
- 8.3.1.9 STEP 9: Run Power up Calibration
- 8.3.1.10 STEP 10: JESD Interface Synchronization
- 8.3.1
Initial Device Configuration After Power-Up
- 8.4 Power Supply Recommendations
- 8.5 Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.3.1.1 Input Bandwidth and Full-Scale
The input bandwidth (-3 dB) and input fullscale are dependent on what input termination and averaging mode are chosen as shown in the summary in Table 7-47. With 2x averaging enabled, the -3 dB bandwidth reduces to ~ 1.5 GHz and 100 Ω differential termination - the bandwidth can be increased by changing the input termination to 50 Ω differential.
| # of ADCs averaged | Input Bandwidth (-3 dB) | Reset Switch | Selected differential input termination | Input Full-scale |
|---|---|---|---|---|
| 1 (Default) | 1.6 GHz | 1 | 100 Ω | + 1 dBm |
| 2 | 1.5 GHz | 1 | + 1.8 dBm | |
| 4 | 1.5 GHz | 1 | +1.8 dBm | |
| 1 | 1.5 GHz | 0 | + 0.5 dBm | |
| 2 | 0.8 GHz | 0 | ||
| 4 | 0.4 GHz | 0 |
There is an internal RESET switch which resets the sampling capacitor to VCM in between samples when enabled. The full power input bandwidth plots with input RESET switch disabled (RSW0) and enabled (RSW1) are shown in Figure 7-2.
Figure 7-2 Full power input bandwidthThe RESET switch is enabled by default and can be disabled with the following register writes:
| ADDR | DATA | DESCRIPTION |
|---|---|---|
| 0x05 | 0x40 | Select ANALOG page |
| 0x6D | 0xC0 | Disable RESET Switch (to enable: 0x00) |
| 0x6E | 0x08 | Disable RESET Switch (to enable: 0x00) |